From: lkcl <lkcl@web>
Date: Fri, 6 May 2022 12:21:34 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2376
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=483752f94d6eca681d1a7ef6cee574ed32c8517f;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index cd6215fa7..27a164ff6 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -542,8 +542,9 @@ to connect to standard DIMMs.
 Extra-V appears to be a remarkable research project that, by leveraging
 OpenCAPI, assuming that the map of edges in any given arbitrary data graph
 could be kept by the main CPU in-memory, could distribute and delegate
-a limited-capability deterministic node-walking schedule actually right down into the memory itself (on the other side of that L1-4 cache barrier),
-where, thanks to the OpenCAPI Standard, many of the nightmare problems
+a limited-capability deterministic but most importantly *data-dependent*
+node-walking schedule actually right down into the memory itself (on the other side of that L1-4 cache barrier).
+Thanks to the OpenCAPI Standard, many of the nightmare problems
 of other more explicit parallel processing paradigms disappear.
 
 **Snitch**