From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 13 Apr 2020 20:11:25 +0000 (-0700)
Subject: aiger: -xaiger to parse initial state back into (* init *) on Q wire
X-Git-Tag: working-ls180~549^2~66
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=483a190c1b468b2a22fe7f2b92075953c6095f7d;p=yosys.git

aiger: -xaiger to parse initial state back into (* init *) on Q wire
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 7e5e6dd2d..ed3a926c6 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -802,7 +802,8 @@ void AigerReader::post_process()
 		ff->setPort(ID::C, r.first->second);
 		ff->setPort(ID::D, d);
 		ff->setPort(ID::Q, q);
-		ff->attributes[ID::abc9_init] = initial_state[i];
+		log_assert(GetSize(q) == 1);
+		q->attributes[ID::init] = initial_state[i];
 	}
 
 	dict<RTLIL::IdString, std::pair<int,int>> wideports_cache;