From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 13 May 2020 18:55:41 +0000 (+0100)
Subject: minor cleanup of shift_rot main_stage
X-Git-Tag: div_pipeline~1256
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=48444249b7ae32453c81b30008f3506896fab572;p=soc.git

minor cleanup of shift_rot main_stage
---

diff --git a/src/soc/shift_rot/main_stage.py b/src/soc/shift_rot/main_stage.py
index e0b453b4..0b782120 100644
--- a/src/soc/shift_rot/main_stage.py
+++ b/src/soc/shift_rot/main_stage.py
@@ -30,6 +30,8 @@ class ShiftRotMainStage(PipeModBase):
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
+
+        # set up microwatt rotator module
         m.submodules.rotator = rotator = Rotator()
         comb += [
             rotator.rs.eq(self.i.rs),
@@ -40,14 +42,7 @@ class ShiftRotMainStage(PipeModBase):
             rotator.arith.eq(self.i.ctx.op.is_signed),
         ]
 
-        # Defaults
-        comb += [rotator.right_shift.eq(0),
-                 rotator.clear_left.eq(0),
-                 rotator.clear_right.eq(0)]
-
-        comb += [self.o.o.eq(rotator.result_o),
-                 self.o.carry_out.eq(rotator.carry_out_o)]
-
+        # instruction rotate type
         with m.Switch(self.i.ctx.op.insn_type):
             with m.Case(InternalOp.OP_SHL):
                 comb += [rotator.right_shift.eq(0),
@@ -62,10 +57,9 @@ class ShiftRotMainStage(PipeModBase):
                         rotator.clear_left.eq(1),
                         rotator.clear_right.eq(1)]
                 
-
-
-
-
+        # outputs from the microwatt rotator module
+        comb += [self.o.o.eq(rotator.result_o),
+                 self.o.carry_out.eq(rotator.carry_out_o)]
 
         ###### sticky overflow and context, both pass-through #####