From: Henry Styles Date: Mon, 14 Aug 2017 23:21:55 +0000 (-0700) Subject: u500vc707devkit 4GB : new address map allows switch to paramterization with address... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=484bb4ff5963f1ac8681eb95dff62fa081ccbd07;p=sifive-blocks.git u500vc707devkit 4GB : new address map allows switch to paramterization with address ranges --- diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala index 7288461..5351cf0 100644 --- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala +++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala @@ -11,26 +11,29 @@ import freechips.rocketchip.tilelink._ import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig} case class XilinxVC707MIGParams( - depthGB : Int + address : Seq[AddressSet] ) -class XilinxVC707MIGPads(depthGB : Integer) extends VC707MIGIODDR(depthGB) +class XilinxVC707MIGPads(depth : BigInt) extends VC707MIGIODDR(depth) { + def this(c : XilinxVC707MIGParams) { + this(AddressRange.fromSets(c.address).head.size) + } +} -class XilinxVC707MIGIO(depthGB : Integer) extends VC707MIGIODDR(depthGB) with VC707MIGIOClocksReset +class XilinxVC707MIGIO(depth : BigInt) extends VC707MIGIODDR(depth) with VC707MIGIOClocksReset class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends LazyModule { - require((c.depthGB == 1) || (c.depthGB == 4)) - - // Suppoted address map configuratons - val address = if(c.depthGB == 1) Seq(AddressSet(0x80000000L , 0x40000000L-1)) //1GB @ 2GB - else Seq(AddressSet(0x80000000L, 0x80000000L-1), //2GB @ 2GB - AddressSet(0x2080000000L, 0x80000000L-1)) //2GB @ 130GB + val ranges = AddressRange.fromSets(c.address) + require (ranges.size == 1, "DDR range must be contiguous") + val offset = ranges.head.base + val depth = ranges.head.size + require((depth==0x40000000L) || (depth==0x100000000L)) //1GB or 4GB depth val device = new MemoryDevice val node = TLInputNode() val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters( slaves = Seq(AXI4SlaveParameters( - address = address, + address = c.address, resources = device.reg, regionType = RegionType.UNCACHED, executable = true, @@ -55,12 +58,12 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L lazy val module = new LazyModuleImp(this) { val io = new Bundle { - val port = new XilinxVC707MIGIO(c.depthGB) + val port = new XilinxVC707MIGIO(depth) val tl = node.bundleIn } //MIG black box instantiation - val blackbox = Module(new vc707mig(c.depthGB)) + val blackbox = Module(new vc707mig(depth)) //pins to top level @@ -109,17 +112,8 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L //app_ref_ack := unconnected //app_zq_ack := unconnected - //if(bits(37)==1) { (upper address range) - // axiaddress = least sig 37 bits of address - //else{ (low address range) - // axiaddress = address ^ 0x8000000 - //} - - val awaddr = axi_async.aw.bits.addr; - val awbit31 = awaddr(37) & awaddr(31) - - val araddr = axi_async.ar.bits.addr; - val arbit31 = araddr(37) & araddr(31) + val awaddr = axi_async.aw.bits.addr - UInt(offset) + val araddr = axi_async.ar.bits.addr - UInt(offset) //slave AXI interface write address ports blackbox.io.s_axi_awid := axi_async.aw.bits.id diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala index 59dd4a0..7aebfae 100644 --- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala +++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala @@ -4,7 +4,7 @@ package sifive.blocks.devices.xilinxvc707mig import Chisel._ import freechips.rocketchip.config._ import freechips.rocketchip.coreplex.HasMemoryBus -import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} +import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp, AddressRange} case object MemoryXilinxDDRKey extends Field[XilinxVC707MIGParams] @@ -27,7 +27,10 @@ trait HasMemoryXilinxVC707MIGBundle { trait HasMemoryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp with HasMemoryXilinxVC707MIGBundle { val outer: HasMemoryXilinxVC707MIG - val xilinxvc707mig = IO(new XilinxVC707MIGIO(p(MemoryXilinxDDRKey).depthGB)) + val ranges = AddressRange.fromSets(p(MemoryXilinxDDRKey).address) + require (ranges.size == 1, "DDR range must be contiguous") + val depth = ranges.head.size + val xilinxvc707mig = IO(new XilinxVC707MIGIO(depth)) xilinxvc707mig <> outer.xilinxvc707mig.module.io.port } diff --git a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala index 0957d53..7b9ace3 100644 --- a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala +++ b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala @@ -9,9 +9,9 @@ import freechips.rocketchip.config._ // IP VLNV: xilinx.com:customize_ip:vc707mig:1.0 // Black Box -class VC707MIGIODDR(depthGB : Integer) extends GenericParameterizedBundle(depthGB) { - require((depthGB==1) || (depthGB==4),"VC707MIGIODDR supports 1GB and 4GB depth configuraton only") - val ddr3_addr = Bits(OUTPUT,if(depthGB==1) 14 else 16) +class VC707MIGIODDR(depth : BigInt) extends GenericParameterizedBundle(depth) { + require((depth==0x40000000L) || (depth==0x100000000L),"VC707MIGIODDR supports 1GB and 4GB depth configuraton only") + val ddr3_addr = Bits(OUTPUT,if(depth==0x40000000L) 14 else 16) val ddr3_ba = Bits(OUTPUT,3) val ddr3_ras_n = Bool(OUTPUT) val ddr3_cas_n = Bool(OUTPUT) @@ -46,13 +46,15 @@ trait VC707MIGIOClocksReset extends Bundle { //scalastyle:off //turn off linter: blackbox name must match verilog module -class vc707mig(depthGB : Integer)(implicit val p:Parameters) extends BlackBox +class vc707mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox { - require((depthGB==1) || (depthGB==4),"vc707mig supports 1GB and 4GB depth configuraton only") + private val oneGB : BigInt = 0x40000000L + private val fourGB : BigInt = 0x100000000L + require((depth==oneGB) || (depth==fourGB),"vc707mig supports 1GB and 4GB depth configuraton only") - override def desiredName = if(depthGB==4) "vc707mig4gb" else "vc707mig" + override def desiredName = if(depth==fourGB) "vc707mig4gb" else "vc707mig" - val io = new VC707MIGIODDR(depthGB) with VC707MIGIOClocksReset { + val io = new VC707MIGIODDR(depth) with VC707MIGIOClocksReset { // User interface signals val app_sr_req = Bool(INPUT) val app_ref_req = Bool(INPUT) @@ -63,7 +65,7 @@ class vc707mig(depthGB : Integer)(implicit val p:Parameters) extends BlackBox //axi_s //slave interface write address ports val s_axi_awid = Bits(INPUT,4) - val s_axi_awaddr = Bits(INPUT,if(depthGB==1) 30 else 32) + val s_axi_awaddr = Bits(INPUT,if(depth==oneGB) 30 else 32) val s_axi_awlen = Bits(INPUT,8) val s_axi_awsize = Bits(INPUT,3) val s_axi_awburst = Bits(INPUT,2) @@ -86,7 +88,7 @@ class vc707mig(depthGB : Integer)(implicit val p:Parameters) extends BlackBox val s_axi_bvalid = Bool(OUTPUT) //slave interface read address ports val s_axi_arid = Bits(INPUT,4) - val s_axi_araddr = Bits(INPUT,if(depthGB==1) 30 else 32) + val s_axi_araddr = Bits(INPUT,if(depth==oneGB) 30 else 32) val s_axi_arlen = Bits(INPUT,8) val s_axi_arsize = Bits(INPUT,3) val s_axi_arburst = Bits(INPUT,2)