From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 15 Jan 2020 00:33:41 +0000 (-0800)
Subject: abc9_ops: cope with (* abc9_flop *) in place of (* abc9_box_id *)
X-Git-Tag: working-ls180~822^2~7
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=485e08e4363f2aa93204f8bcc6c1ff5243936ea6;p=yosys.git

abc9_ops: cope with (* abc9_flop *) in place of (* abc9_box_id *)
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index c2d076c86..66ddbde33 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -318,7 +318,7 @@ struct XAigerWriter
 
 			RTLIL::Module* box_module = module->design->module(cell->type);
 			log_assert(box_module);
-			log_assert(box_module->attributes.count("\\abc9_box_id"));
+			log_assert(box_module->attributes.count("\\abc9_box_id") || box_module->get_bool_attribute("\\abc9_flop"));
 
 			auto r = box_ports.insert(cell->type);
 			if (r.second) {
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 4d05b5afb..fd2759ae5 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -117,7 +117,7 @@ void check(RTLIL::Design *design)
 				if (wire->port_output) num_outputs++;
 			}
 			if (num_outputs != 1)
-				log_error("Module '%s' with (* abc_flop *) has %d outputs (expect 1).\n", log_id(m), num_outputs);
+				log_error("Module '%s' with (* abc9_flop *) has %d outputs (expect 1).\n", log_id(m), num_outputs);
 		}
 	}
 }
@@ -333,7 +333,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 		log_assert(cell);
 
 		RTLIL::Module* box_module = design->module(cell->type);
-		if (!box_module || !box_module->attributes.count("\\abc9_box_id"))
+		if (!box_module || (!box_module->attributes.count("\\abc9_box_id") && !box_module->get_bool_attribute("\\abc9_flop")))
 			continue;
 
 		cell->attributes["\\abc9_box_seq"] = box_count++;