From: Shriya Sharma Date: Tue, 19 Sep 2023 15:40:30 +0000 (+0100) Subject: Added english description for lbzu instruction X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=486fc66860f7652c5b856c8956815587d5ef3e2d;p=openpower-isa.git Added english description for lbzu instruction --- diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn index 71059cb0..500489b7 100644 --- a/openpower/isa/fixedload.mdwn +++ b/openpower/isa/fixedload.mdwn @@ -76,6 +76,12 @@ Pseudo-code: RT <- ([0] * (XLEN-8)) || MEM(EA, 1) RA <- EA +Description:Let the effective address (EA) be the sum (RA)+ D. The +byte in storage addressed by EA is loaded into RT 56:63. +RT0:55 are set to 0. +EA is placed into register RA. +If RA=0 or RA=RT, the instruction form is invalid. + Special Registers Altered: None