From: klehman <klehman9@comcast.net>
Date: Tue, 7 Sep 2021 15:47:32 +0000 (-0400)
Subject: added assertion to regression_rlwnm
X-Git-Tag: DRAFT_SVP64_0_1~23
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=48701f69cf040b06f60b858e3ae047b0557ea9dc;p=openpower-isa.git

added assertion to regression_rlwnm
---

diff --git a/src/openpower/decoder/isa/test_caller_shift_rot.py b/src/openpower/decoder/isa/test_caller_shift_rot.py
index c143c1a9..e0e32056 100644
--- a/src/openpower/decoder/isa/test_caller_shift_rot.py
+++ b/src/openpower/decoder/isa/test_caller_shift_rot.py
@@ -16,6 +16,7 @@ class DecoderTestCase(FHDLTestCase):
         initial_regs[2] = 11
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, initial_regs)
+            self.assertEqual(sim.gpr(3), SelectableInt(0x8800, 64))
 
     def test_case_srw_1(self):
         lst = ["sraw 3, 1, 2"]