From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 8 Apr 2018 07:51:47 +0000 (+0100)
Subject: add RVV ISA table
X-Git-Tag: convert-csv-opcode-to-binary~5724
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=487462c6fc69142a3a82949b802794cd5fcc9270;p=libreriscv.git

add RVV ISA table
---

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index b3fcc8362..9135a611d 100644
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -521,6 +521,67 @@ Exceptions are:
   VSRL, VSRA, VEIDX, VFIRST, VSGNJN, VFSGNJX and potentially more.
 * Consensual Jump
 
+Table of RV32V Instructions
+
+| RV32V      |     |
+| -----      | --- |
+| VADD       |     |
+| VSUB       |     |
+| VSL        |     |
+| VSR        |     |
+| VAND       |     |
+| VOR        |     |
+| VXOR       |     |
+| VSEQ       |     |
+| VSNE       |     |
+| VSLT       |     |
+| VSGE       |     |
+| VCLIP      |     |
+| VCVT       |     |
+| VMPOP      |     |
+| VMFIRST    |     |
+| VEXTRACT   |     |
+| VINSERT    |     |
+| VMERGE     |     |
+| VSELECT    |     |
+| VSLIDE     |     |
+| VDIV       |     |
+| VREM       |     |
+| VMUL       |     |
+| VMULH      |     |
+| VMIN       |     |
+| VMAX       |     |
+| VSGNJ      |     |
+| VSGNJN     |     |
+| VSGNJX     |     |
+| VSQRT      |     |
+| VCLASS     |     |
+| VPOPC      |     |
+| VADDI      |     |
+| VSLI       |     |
+| VSRI       |     |
+| VANDI      |     |
+| VORI       |     |
+| VXORI      |     |
+| VCLIPI     |     |
+| VMADD      |     |
+| VMSUB      |     |
+| VNMADD     |     |
+| VNMSUB     |     |
+| VLD        |     |
+| VLDS       |     |
+| VLDX       |     |
+| VST        |     |
+| VSTS       |     |
+| VSTX       |     |
+| VAMOSWAP   |     |
+| VAMOADD    |     |
+| VAMOAND    |     |
+| VAMOOR     |     |
+| VAMOXOR    |     |
+| VAMOMIN    |     |
+| VAMOMAX    |     |
+
 ## TODO: sort
 
 > I suspect that the "hardware loop" in question is actually a zero-overhead