From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 07:24:22 +0000 (+0200)
Subject: Split latches into separete tests
X-Git-Tag: working-ls180~990^2~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=487b38b124cbb388bd680cb54cb43c58829ca1d3;p=yosys.git

Split latches into separete tests
---

diff --git a/tests/xilinx/latches.v b/tests/xilinx/latches.v
index 9dc43e4c2..adb5d5319 100644
--- a/tests/xilinx/latches.v
+++ b/tests/xilinx/latches.v
@@ -22,37 +22,3 @@ module latchsr
 		else if ( en )
 			q <= d;
 endmodule
-
-
-module top (
-input clk,
-input clr,
-input pre,
-input a,
-output b,b1,b2
-);
-
-
-latchp u_latchp (
-        .en (clk ),
-        .d (a ),
-        .q (b )
-    );
-
-
-latchn u_latchn (
-        .en (clk ),
-        .d (a ),
-        .q (b1 )
-    );
-
-
-latchsr u_latchsr (
-        .en (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b2 )
-    );
-
-endmodule
diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
index 795ac9074..68ca42b10 100644
--- a/tests/xilinx/latches.ys
+++ b/tests/xilinx/latches.ys
@@ -2,15 +2,34 @@ read_verilog latches.v
 design -save read
 
 proc
-async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
-flatten
+hierarchy -top latchp
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd latchp # Constrain all select calls below inside the top module
+select -assert-count 1 t:LDCE
 
-synth_xilinx
-flatten
-cd top
+select -assert-none t:LDCE %% t:* %D
+
+
+design -load read
+proc
+hierarchy -top latchn
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd latchn # Constrain all select calls below inside the top module
+select -assert-count 1 t:LDCE
 select -assert-count 1 t:LUT1
+
+select -assert-none t:LDCE t:LUT1 %% t:* %D
+
+
+design -load read
+proc
+hierarchy -top latchsr
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd latchsr # Constrain all select calls below inside the top module
+select -assert-count 1 t:LDCE
 select -assert-count 2 t:LUT3
-#Xilinx Vivado synthesizes LDCE cell for this case. Need support it.
-select -assert-count 3 t:$_DLATCH_P_
-select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D
+
+select -assert-none t:LDCE t:LUT3 %% t:* %D