From: whitequark <whitequark@whitequark.org>
Date: Sat, 11 Jul 2020 12:25:31 +0000 (+0000)
Subject: sim.pysim: use VCD aliases to reduce space and time overhead.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=487e8d89dc132ef05efae3709572e2e525742ff4;p=nmigen.git

sim.pysim: use VCD aliases to reduce space and time overhead.

On Minerva SoC, this reduces VCD file size by about 35%, and reduces
runtime overhead of writing VCDs by 10% or less.
---

diff --git a/nmigen/sim/pysim.py b/nmigen/sim/pysim.py
index 9dde345..166e2a1 100644
--- a/nmigen/sim/pysim.py
+++ b/nmigen/sim/pysim.py
@@ -111,23 +111,25 @@ class _VCDWaveformWriter(_WaveformWriter):
                             var_name_suffix = var_name
                         else:
                             var_name_suffix = "{}${}".format(var_name, suffix)
-                        vcd_var = self.vcd_writer.register_var(
-                            scope=var_scope, name=var_name_suffix,
-                            var_type=var_type, size=var_size, init=var_init)
+                        if signal not in self.vcd_vars:
+                            vcd_var = self.vcd_writer.register_var(
+                                scope=var_scope, name=var_name_suffix,
+                                var_type=var_type, size=var_size, init=var_init)
+                            self.vcd_vars[signal] = vcd_var
+                        else:
+                            self.vcd_writer.register_alias(
+                                scope=var_scope, name=var_name_suffix,
+                                var=self.vcd_vars[signal])
                         break
                     except KeyError:
                         suffix = (suffix or 0) + 1
 
-                if signal not in self.vcd_vars:
-                    self.vcd_vars[signal] = set()
-                self.vcd_vars[signal].add(vcd_var)
-
                 if signal not in self.gtkw_names:
                     self.gtkw_names[signal] = (*var_scope, var_name_suffix)
 
     def update(self, timestamp, signal, value):
-        vcd_vars = self.vcd_vars.get(signal)
-        if vcd_vars is None:
+        vcd_var = self.vcd_vars.get(signal)
+        if vcd_var is None:
             return
 
         vcd_timestamp = self.timestamp_to_vcd(timestamp)
@@ -135,8 +137,7 @@ class _VCDWaveformWriter(_WaveformWriter):
             var_value = self.decode_to_vcd(signal, value)
         else:
             var_value = value
-        for vcd_var in vcd_vars:
-            self.vcd_writer.change(vcd_var, vcd_timestamp, var_value)
+        self.vcd_writer.change(vcd_var, vcd_timestamp, var_value)
 
     def close(self, timestamp):
         if self.vcd_writer is not None:
diff --git a/setup.py b/setup.py
index 3d91154..3c05da3 100644
--- a/setup.py
+++ b/setup.py
@@ -27,7 +27,7 @@ setup(
     install_requires=[
         "importlib_metadata; python_version<'3.8'",  # for __version__ and nmigen._yosys
         "importlib_resources; python_version<'3.9'", # for nmigen._yosys
-        "pyvcd~=0.2.0", # for nmigen.pysim
+        "pyvcd~=0.2.2", # for nmigen.pysim
         "Jinja2~=2.11", # for nmigen.build
     ],
     extras_require={