From: Nathanael Premillieu <nathananel.premillieu@arm.com>
Date: Sun, 22 Nov 2015 10:10:19 +0000 (-0500)
Subject: cpu: Fix base FP and CC register index in o3 insertThread()
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=488128dab2b9fb728466ade9dd54f9613ee03880;p=gem5.git

cpu: Fix base FP and CC register index in o3 insertThread()

Note that the method is not used, and could possibly be deleted.
---

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index c17b7a9dc..665654f68 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -790,8 +790,8 @@ FullO3CPU<Impl>::insertThread(ThreadID tid)
     }
 
     //Bind Float Regs to Rename Map
-    int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
-    for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) {
+    int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs;
+    for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) {
         PhysRegIndex phys_reg = freeList.getFloatReg();
 
         renameMap[tid].setEntry(freg,phys_reg);
@@ -799,8 +799,8 @@ FullO3CPU<Impl>::insertThread(ThreadID tid)
     }
 
     //Bind condition-code Regs to Rename Map
-    max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs;
-    for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
+    max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs;
+    for (int creg = TheISA::CC_Reg_Base;
          creg < max_reg; creg++) {
         PhysRegIndex phys_reg = freeList.getCCReg();