From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Apr 2019 18:19:52 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into xaig
X-Git-Tag: working-ls180~1237^2~169
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4883391b6331e62226c46e797f82a31ef9ef81a3;p=yosys.git

Merge remote-tracking branch 'origin/master' into xaig
---

4883391b6331e62226c46e797f82a31ef9ef81a3
diff --cc frontends/aiger/aigerparse.cc
index db5f9d2b9,2e4774dfd..4e3f5e7c9
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@@ -35,11 -33,8 +35,8 @@@
  
  YOSYS_NAMESPACE_BEGIN
  
- //#define log_debug log
- #define log_debug(...) ;
- 
 -AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name)
 -    : design(design), f(f), clk_name(clk_name)
 +AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports)
 +    : design(design), f(f), clk_name(clk_name), map_filename(map_filename), wideports(wideports)
  {
      module = new RTLIL::Module;
      module->name = module_name;
diff --cc techlibs/xilinx/synth_xilinx.cc
index 8a531c497,d66722195..08d74cd3b
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -277,14 -276,9 +284,9 @@@ struct SynthXilinxPass : public Pas
  		if (check_label(active, run_from, run_to, "map_luts"))
  		{
  			Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?");
 -			Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 +			Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
  			Pass::call(design, "clean");
  			Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
- 		}
- 
- 		if (check_label(active, run_from, run_to, "map_cells"))
- 		{
- 			Pass::call(design, "techmap -map +/xilinx/cells_map.v");
  			Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
  					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
  			Pass::call(design, "clean");