From: Ron Dreslinski <rdreslin@umich.edu>
Date: Sun, 3 Apr 2005 01:36:08 +0000 (-0500)
Subject: Added support for multiple prefetch address from single access (depth of prefetch... 
X-Git-Tag: m5_1.0_tutorial~65^2~12^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4889d8f78826331d567327535fcd481fa2caf939;p=gem5.git

Added support for multiple prefetch address from single access (depth of prefetch) also added the ability to squash some prefetchs to match the GHB technique

python/m5/objects/BaseCache.mpy:
    Added parameters

--HG--
extra : convert_revision : 92b646eb61455d283a5c2ac0b3f8fbd62e39fb87
---

diff --git a/python/m5/objects/BaseCache.mpy b/python/m5/objects/BaseCache.mpy
index 198665325..3727f2f01 100644
--- a/python/m5/objects/BaseCache.mpy
+++ b/python/m5/objects/BaseCache.mpy
@@ -1,5 +1,7 @@
 from BaseMem import BaseMem
 
+class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
+
 simobj BaseCache(BaseMem):
     type = 'BaseCache'
     adaptive_compression = Param.Bool(False,
@@ -44,4 +46,11 @@ simobj BaseCache(BaseMem):
          "Number of entries in the harware prefetch queue")
     prefetch_past_page = Param.Bool(False,
          "Allow prefetches to cross virtual page boundaries")
-
+    prefetch_serial_squash = Param.Bool(False,
+         "Squash prefetches with a later time on a subsequent miss")
+    prefetch_degree = Param.Int(1,
+         "Degree of the prefetch depth")
+    prefetch_latency = Param.Tick(10,
+         "Latency of the prefetcher")
+    prefetch_policy = Param.Prefetch('none',
+         "Type of prefetcher to use")