From: lkcl <lkcl@web>
Date: Thu, 30 Mar 2023 11:54:09 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls012_v1~211
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=488d3c93cdc87f31acf0cd5ee16f94cfc9f6f24e;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index ceb6848a3..0e051d834 100644
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -252,6 +252,33 @@ effect i.e. under these circumstances (EXTRA=0) the register field names
 RA, RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers.
 This is part of `scalar identity behaviour` described above.
 
+**Condition Register(s)**
+
+The Scalar Power ISA Condition Register is a 64 bit register where the top
+32 MSBs (numbered 0:31 in MSB0 numbering) are not used.  This convention is
+*preserved* (not modified, respected, and thus coipied)
+in SVP64 and an additional 15 Condition Registers provided in
+order to store the new CR Fields, CR8-CR15, CR16-CR23 etc. sequentially.
+The top 32 MSBs in each new SVP64 Condition Register are *also* not used:
+only the bottom 32 bits (numbered 32:63 in MSB0 numbering).
+
+*Programmer's note: using `sv.mfcr` without element-width overrides to take
+into account the fact that the top 32 MSBs are zero and thus effectively
+doubling the number of GPR registers required to hold all 128 CR Fields
+would seem the only option because normally elwidth overrides would
+halve the capacity of the instruction.  However in this case it is
+possible to use destination element-width overrides (for `sv.mfcr`.
+source overrides would be used on the GPR of `sv.mtocrf`),
+whereupon truncation
+of the 64-bit Condition Register(s) occurs, throwing away the zeros and
+storing the remaining (valid, desired) 32-bit values sequentially into
+(LSB0-convention) lower-numbered and upper-numbered halves of GPRs respectively.
+The programmer is expected to be aware however that the full width of
+the entire 64-bit Condition Register is considered to be "an element".
+This is **not** like any other Condition-Register instructions because
+all other CR instructions, on closer investigation, will be observed
+to all be CR-bit or CR-Field related. Thus `VL` of 16 must be used*
+
 ## Future expansion.
 
 With the way that EXTRA fields are defined and applied to register fields,