From: SergeyDegtyar <sndegtyar@gmail.com>
Date: Tue, 10 Sep 2019 05:36:59 +0000 (+0300)
Subject: Fix latches.ys test
X-Git-Tag: working-ls180~990^2~25
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=489444bcba0d54a45605872eb466792f07357f84;p=yosys.git

Fix latches.ys test
---

diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
index 9ab562bcf..042ee2d4f 100644
--- a/tests/xilinx/latches.ys
+++ b/tests/xilinx/latches.ys
@@ -11,10 +11,9 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 design -load read
 
 synth_xilinx
-#cd top
-
+flatten
+cd top
 select -assert-count 1 t:LUT1
 select -assert-count 2 t:LUT3
 select -assert-count 3 t:$_DLATCH_P_
-#ERROR: Assertion failed: selection is not empty: t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D
-#select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D
+select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D