From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 27 Jul 2018 06:25:52 +0000 (+0100)
Subject: add flexbus get/put link
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=48993171d8f12bd30d5921e86310248d343ef151;p=pinmux.git

add flexbus get/put link
---

diff --git a/src/bsv/bsv_lib/soc_template.bsv b/src/bsv/bsv_lib/soc_template.bsv
index e99b9b1..66cab5e 100644
--- a/src/bsv/bsv_lib/soc_template.bsv
+++ b/src/bsv/bsv_lib/soc_template.bsv
@@ -213,6 +213,9 @@ package Soc;
                               vme.slave_axi_vme);
             `endif
 
+//          pin connections
+{9}
+
             // fabric connections
 {5}
 
diff --git a/src/bsv/peripheral_gen/flexbus.py b/src/bsv/peripheral_gen/flexbus.py
index 1de5141..8fed547 100644
--- a/src/bsv/peripheral_gen/flexbus.py
+++ b/src/bsv/peripheral_gen/flexbus.py
@@ -24,20 +24,33 @@ class flexbus(PBase):
     def _mk_connection(self, name=None, count=0):
         return "fb{0}.axi_side"
 
+    def pinname_in(self, pname):
+        return {'ta': 'flexbus_side.tAn',
+               }.get(pname, '')
+
     def pinname_out(self, pname):
-        if pname in ['cmd', 'clk']:
-            return pname
-        return ''
+        return {'ale': 'flexbus_side.m_ALE',
+                'oe' : 'flexbus_side.m_OEn',
+                'rw' : 'flexbus_side.m_R_Wn',
+               }.get(pname, '')
 
     def mk_pincon(self, name, count):
         ret = [PBase.mk_pincon(self, name, count)]
         # special-case for gpio in, store in a temporary vector
         plen = len(self.peripheral.pinspecs)
-        template = "mkConnection({0}.{1},\n\t\t\t{2}.{1});"
+        template = "mkConnection({0}.{3},\n\t\t\t{2}.flexbus_side.{1});"
         sname = self.peripheral.iname().format(count)
         name = self.get_iname(count)
         ps = "pinmux.peripheral_side.%s" % sname
         n = "{0}".format(name)
-        for ptype in ['out', 'out_en', 'in']:
-            ret.append(template.format(ps, ptype, n))
+        for stype, ptype in [
+                ('cs', 'm_FBCSn'),
+                ('bwe', 'm_BWEn'),
+                ('tbst', 'm_TBSTn'),
+                ('tsiz', 'm_TSIZ'),
+                ('ad_in', 'm_AD'),
+                ('ad_out', 'm_din'),
+                ('ad_en', 'm_OE32n'),
+            ]:
+            ret.append(template.format(ps, ptype, n, stype))
         return '\n'.join(ret)
diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py
index 03ee609..12c2813 100644
--- a/src/bsv/pinmux_generator.py
+++ b/src/bsv/pinmux_generator.py
@@ -155,6 +155,7 @@ def write_soc(soc, soct, p, ifaces, iocells):
         bsv_file.write(soct.format(imports, ifdecl, mkfast,
                                    slavedecl, mastdecl, mkcon,
                                    inst, dma, num_dmachannels,
+                                   pincon,
                                    ))
 
 
diff --git a/src/spec/i_class.py b/src/spec/i_class.py
index e118989..3e4b678 100644
--- a/src/spec/i_class.py
+++ b/src/spec/i_class.py
@@ -86,7 +86,7 @@ def pinspec():
 
     # see comment in spec.interfaces.PinGen, this is complicated.
     flexspec = {
-        'FB_TS': ('FB_ALE', 2),
+        #'FB_TS': ('FB_ALE', 2), # commented out for now
         'FB_CS2': ('FB_BWE2', 2),
         'FB_AD0': ('FB_BWE2', 3),
         'FB_CS3': ('FB_BWE3', 2),
diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py
index 5761186..06c6504 100644
--- a/src/spec/pinfunctions.py
+++ b/src/spec/pinfunctions.py
@@ -144,7 +144,8 @@ def flexbus1(suffix, bank):
     for i in range(2):
         buspins.append("CS%d+" % i)
     buspins += ['ALE+', 'OE+', 'RW+', 'TA-',
-                'TS+', 'TBST+',
+                # 'TS+',  commented out for now, mirrors ALE, for mux'd mode
+                'TBST+',
                 'TSIZ0+', 'TSIZ1+']
     for i in range(4):
         buspins.append("BWE%d+" % i)