From: Vinson Lee Date: Sat, 21 Aug 2010 21:29:50 +0000 (-0700) Subject: nvfx: Fix SCons build. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=489c787b80064b590016eecf2b8157760b0bc8a2;p=mesa.git nvfx: Fix SCons build. Move declarations before code. Fix void pointer arithmetic. --- diff --git a/src/gallium/drivers/nvfx/nv04_2d.c b/src/gallium/drivers/nvfx/nv04_2d.c index b2f2ae79e12..46d5f5c08d4 100644 --- a/src/gallium/drivers/nvfx/nv04_2d.c +++ b/src/gallium/drivers/nvfx/nv04_2d.c @@ -257,6 +257,9 @@ nv04_region_assert(struct nv04_region* rgn, unsigned w, unsigned h) static inline int nv04_region_is_contiguous(struct nv04_region* rgn, int w, int h) { + int surf_min; + int rect_min; + if(rgn->pitch) return rgn->pitch == w << rgn->bpps; @@ -275,8 +278,8 @@ nv04_region_is_contiguous(struct nv04_region* rgn, int w, int h) if(rgn->d > 1) return 0; - int surf_min = MIN2(rgn->w, rgn->h); - int rect_min = MIN2(w, h); + surf_min = MIN2(rgn->w, rgn->h); + rect_min = MIN2(w, h); if((rect_min == surf_min) || (w == h) || (w == 2 * h)) return 1; @@ -361,8 +364,10 @@ nv04_region_do_align_offset(struct nv04_region* rgn, unsigned w, unsigned h, int { if(rgn->pitch > 0) { + int delta; + assert(!(rgn->offset & ((1 << rgn->bpps) - 1))); // fatal! - int delta = rgn->offset & ((1 << shift) - 1); + delta = rgn->offset & ((1 << shift) - 1); if(h <= 1) { @@ -388,19 +393,22 @@ nv04_region_do_align_offset(struct nv04_region* rgn, unsigned w, unsigned h, int } else { + int size; + int min; + int v; + // we don't care about the alignment of 3D surfaces since the 2D engine can't use them if(rgn->d < 0) return -1; - int size; - int min = MIN2(rgn->w, rgn->h); + min = MIN2(rgn->w, rgn->h); size = min * min << rgn->bpps; // this is unfixable, and should not be happening if(rgn->offset & (size - 1)) return -1; - int v = (rgn->offset & ((1 << shift) - 1)) / size; + v = (rgn->offset & ((1 << shift) - 1)) / size; rgn->offset -= v * size; if(rgn->h == min) @@ -457,6 +465,10 @@ nv04_region_align(struct nv04_region* rgn, unsigned w, unsigned h, int shift) void nv04_region_copy_cpu(struct nv04_region* dst, struct nv04_region* src, int w, int h) { + uint8_t* mdst; + uint8_t* msrc; + int size; + if(dst->bo != src->bo) { nouveau_bo_map(dst->bo, NOUVEAU_BO_WR); @@ -465,10 +477,10 @@ nv04_region_copy_cpu(struct nv04_region* dst, struct nv04_region* src, int w, in else nouveau_bo_map(dst->bo, NOUVEAU_BO_WR | NOUVEAU_BO_RD); - uint8_t* mdst = dst->bo->map + dst->offset; - uint8_t* msrc = src->bo->map + src->offset; + mdst = (uint8_t*)dst->bo->map + dst->offset; + msrc = (uint8_t*)src->bo->map + src->offset; - int size = w << dst->bpps; + size = w << dst->bpps; nv04_region_assert(dst, w, h); nv04_region_assert(src, w, h); @@ -548,6 +560,7 @@ simple: int* dswy; int* sswx; int* sswy; + int dir; if(!dst->pitch) { @@ -569,7 +582,7 @@ simple: sswy[iy] = nv04_swizzle_bits(0, src->y + iy, src->z, src->w, src->h, src->d); } - int dir = 1; + dir = 1; /* do backwards copies for overlapping swizzled surfaces */ if(dst->pitch == src->pitch && dst->offset == src->offset) { @@ -611,7 +624,7 @@ simple: void nv04_region_fill_cpu(struct nv04_region* dst, int w, int h, unsigned value) { - uint8_t* mdst = (nouveau_bo_map(dst->bo, NOUVEAU_BO_WR), dst->bo->map + dst->offset); + uint8_t* mdst = (nouveau_bo_map(dst->bo, NOUVEAU_BO_WR), (uint8_t*)dst->bo->map + dst->offset); #ifdef NV04_REGION_DEBUG fprintf(stderr, "\tRGN_FILL_CPU "); @@ -727,11 +740,12 @@ nv04_region_copy_swizzle(struct nv04_2d_context *ctx, unsigned ex = (dst->x + w - 1) >> max_shift; unsigned ey = (dst->y + h - 1) >> max_shift; unsigned chunks = (ex - sx + 1) * (ey - sy + 1); + unsigned chunk_size; if(dst->w < cw) cw = dst->w; if(dst->h < ch) ch = dst->h; - unsigned chunk_size = cw * ch << dst->bpps; + chunk_size = cw * ch << dst->bpps; #ifdef NV04_REGION_DEBUG fprintf(stderr, "\tRGN_COPY_SWIZZLE [%i, %i: %i] ", w, h, dst->bpps); @@ -770,10 +784,12 @@ nv04_region_copy_swizzle(struct nv04_2d_context *ctx, for (int cx = sx; cx <= ex; ++cx) { int rx = MAX2(0, (int)(dst->x - cw * cx)); int rw = MIN2((int)cw, (int)(dst->x - cw * cx + w)) - rx; + unsigned dst_offset; + unsigned src_offset; BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_OFFSET, 1); - unsigned dst_offset = dst->offset + (nv04_swizzle_bits_2d(cx * cw, cy * ch, dst->w, dst->h) << dst->bpps); + dst_offset = dst->offset + (nv04_swizzle_bits_2d(cx * cw, cy * ch, dst->w, dst->h) << dst->bpps); assert(dst_offset <= dst->bo->size); assert(dst_offset + chunk_size <= dst->bo->size); OUT_RELOCl(chan, dst->bo, dst_offset, @@ -795,7 +811,7 @@ nv04_region_copy_swizzle(struct nv04_2d_context *ctx, OUT_RING (chan, src->pitch | NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER | NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE); - unsigned src_offset = src->offset + (cy * ch + ry + src->y - dst->y) * src->pitch + ((cx * cw + rx + src->x - dst->x) << src->bpps); + src_offset = src->offset + (cy * ch + ry + src->y - dst->y) * src->pitch + ((cx * cw + rx + src->x - dst->x) << src->bpps); assert(src_offset <= src->bo->size); assert(src_offset + (src->pitch * (rh - 1)) + (rw << src->bpps) <= src->bo->size); OUT_RELOCl(chan, src->bo, src_offset, diff --git a/src/gallium/drivers/nvfx/nvfx_buffer.c b/src/gallium/drivers/nvfx/nvfx_buffer.c index 89bb8570efd..041099e0e56 100644 --- a/src/gallium/drivers/nvfx/nvfx_buffer.c +++ b/src/gallium/drivers/nvfx/nvfx_buffer.c @@ -89,7 +89,7 @@ void nvfx_buffer_upload(struct nvfx_buffer* buffer) // TODO: may want to use a temporary in some cases nouveau_bo_map(buffer->base.bo, NOUVEAU_BO_WR | (buffer->dirty_unsynchronized ? NOUVEAU_BO_NOSYNC : 0)); - memcpy(buffer->base.bo->map + buffer->dirty_begin, buffer->data + buffer->dirty_begin, dirty); + memcpy((uint8_t*)buffer->base.bo->map + buffer->dirty_begin, buffer->data + buffer->dirty_begin, dirty); nouveau_bo_unmap(buffer->base.bo); buffer->dirty_begin = buffer->dirty_end = 0; } diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c index dc681f4d4d2..6c8f5c4708e 100644 --- a/src/gallium/drivers/nvfx/nvfx_fragprog.c +++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c @@ -244,12 +244,13 @@ nv40_fp_if(struct nvfx_fpc *fpc, struct nvfx_src src) { const struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0)); struct nvfx_insn insn = arith(0, MOV, none.reg, NVFX_FP_MASK_X, src, none, none); + uint32_t *hw; insn.cc_update = 1; nvfx_fp_emit(fpc, insn); fpc->inst_offset = fpc->fp->insn_len; grow_insns(fpc, 4); - uint32_t *hw = &fpc->fp->insn[fpc->inst_offset]; + hw = &fpc->fp->insn[fpc->inst_offset]; /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */ hw[0] = (NV40_FP_OP_BRA_OPCODE_IF << NVFX_FP_OP_OPCODE_SHIFT) | NV40_FP_OP_OUT_NONE | @@ -270,9 +271,10 @@ static void nv40_fp_cal(struct nvfx_fpc *fpc, unsigned target) { struct nvfx_label_relocation reloc; + uint32_t *hw; fpc->inst_offset = fpc->fp->insn_len; grow_insns(fpc, 4); - uint32_t *hw = &fpc->fp->insn[fpc->inst_offset]; + hw = &fpc->fp->insn[fpc->inst_offset]; /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */ hw[0] = (NV40_FP_OP_BRA_OPCODE_CAL << NVFX_FP_OP_OPCODE_SHIFT); /* Use .xxxx swizzle so that we check only src[0].x*/ @@ -288,9 +290,10 @@ nv40_fp_cal(struct nvfx_fpc *fpc, unsigned target) static void nv40_fp_ret(struct nvfx_fpc *fpc) { + uint32_t *hw; fpc->inst_offset = fpc->fp->insn_len; grow_insns(fpc, 4); - uint32_t *hw = &fpc->fp->insn[fpc->inst_offset]; + hw = &fpc->fp->insn[fpc->inst_offset]; /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */ hw[0] = (NV40_FP_OP_BRA_OPCODE_RET << NVFX_FP_OP_OPCODE_SHIFT); /* Use .xxxx swizzle so that we check only src[0].x*/ @@ -304,9 +307,10 @@ static void nv40_fp_rep(struct nvfx_fpc *fpc, unsigned count, unsigned target) { struct nvfx_label_relocation reloc; + uint32_t *hw; fpc->inst_offset = fpc->fp->insn_len; grow_insns(fpc, 4); - uint32_t *hw = &fpc->fp->insn[fpc->inst_offset]; + hw = &fpc->fp->insn[fpc->inst_offset]; /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */ hw[0] = (NV40_FP_OP_BRA_OPCODE_REP << NVFX_FP_OP_OPCODE_SHIFT) | NV40_FP_OP_OUT_NONE | @@ -330,9 +334,10 @@ static void nv40_fp_bra(struct nvfx_fpc *fpc, unsigned target) { struct nvfx_label_relocation reloc; + uint32_t *hw; fpc->inst_offset = fpc->fp->insn_len; grow_insns(fpc, 4); - uint32_t *hw = &fpc->fp->insn[fpc->inst_offset]; + hw = &fpc->fp->insn[fpc->inst_offset]; /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */ hw[0] = (NV40_FP_OP_BRA_OPCODE_IF << NVFX_FP_OP_OPCODE_SHIFT) | NV40_FP_OP_OUT_NONE | @@ -353,9 +358,10 @@ nv40_fp_bra(struct nvfx_fpc *fpc, unsigned target) static void nv40_fp_brk(struct nvfx_fpc *fpc) { + uint32_t *hw; fpc->inst_offset = fpc->fp->insn_len; grow_insns(fpc, 4); - uint32_t *hw = &fpc->fp->insn[fpc->inst_offset]; + hw = &fpc->fp->insn[fpc->inst_offset]; /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */ hw[0] = (NV40_FP_OP_BRA_OPCODE_BRK << NVFX_FP_OP_OPCODE_SHIFT) | NV40_FP_OP_OUT_NONE; @@ -778,20 +784,22 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc, case TGSI_OPCODE_ELSE: { + uint32_t *hw; if(!nvfx->is_nv4x) goto nv3x_cflow; assert(util_dynarray_contains(&fpc->if_stack, unsigned)); - uint32_t *hw = &fpc->fp->insn[util_dynarray_top(&fpc->if_stack, unsigned)]; + hw = &fpc->fp->insn[util_dynarray_top(&fpc->if_stack, unsigned)]; hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH | fpc->fp->insn_len; break; } case TGSI_OPCODE_ENDIF: { + uint32_t *hw; if(!nvfx->is_nv4x) goto nv3x_cflow; assert(util_dynarray_contains(&fpc->if_stack, unsigned)); - uint32_t *hw = &fpc->fp->insn[util_dynarray_pop(&fpc->if_stack, unsigned)]; + hw = &fpc->fp->insn[util_dynarray_pop(&fpc->if_stack, unsigned)]; if(!hw[2]) hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH | fpc->fp->insn_len; hw[3] = fpc->fp->insn_len; @@ -1097,6 +1105,8 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx) struct nouveau_channel* chan = nvfx->screen->base.channel; struct nvfx_fragment_program *fp = nvfx->fragprog; int update = 0; + struct nvfx_vertex_program* vp; + unsigned sprite_coord_enable; if (!fp->translated) { @@ -1135,13 +1145,14 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx) if (nvfx->dirty & (NVFX_NEW_FRAGCONST | NVFX_NEW_FRAGPROG)) update = TRUE; - struct nvfx_vertex_program* vp = nvfx->render_mode == HW ? nvfx->vertprog : nvfx->swtnl.vertprog; + vp = nvfx->render_mode == HW ? nvfx->vertprog : nvfx->swtnl.vertprog; if (fp->last_vp_id != vp->id) { char* vp_sem_table = vp->generic_to_fp_input; unsigned char* fp_semantics = fp->slot_to_generic; unsigned diff = 0; + unsigned char* cur_slots; fp->last_vp_id = nvfx->vertprog->id; - unsigned char* cur_slots = fp->slot_to_fp_input; + cur_slots = fp->slot_to_fp_input; for(unsigned i = 0; i < fp->num_slots; ++i) { unsigned char slot_mask = vp_sem_table[fp_semantics[i]]; diff |= (slot_mask >> 4) & (slot_mask ^ cur_slots[i]); @@ -1161,7 +1172,7 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx) } // last_sprite_coord_enable - unsigned sprite_coord_enable = nvfx->rasterizer->pipe.point_quad_rasterization * nvfx->rasterizer->pipe.sprite_coord_enable; + sprite_coord_enable = nvfx->rasterizer->pipe.point_quad_rasterization * nvfx->rasterizer->pipe.sprite_coord_enable; if(fp->last_sprite_coord_enable != sprite_coord_enable) { unsigned texcoord_mask = vp->texcoord_ouput_mask; @@ -1199,6 +1210,9 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx) } if(update) { + int offset; + uint32_t* fpmap; + ++fp->bo_prog_idx; if(fp->bo_prog_idx >= fp->progs_per_bo) { @@ -1209,6 +1223,9 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx) else { struct nvfx_fragment_program_bo* fpbo = os_malloc_aligned(sizeof(struct nvfx_fragment_program) + (fp->prog_size + 8) * fp->progs_per_bo, 16); + uint8_t* map; + uint8_t* buf; + fpbo->slots = (unsigned char*)&fpbo->insn[(fp->prog_size) * fp->progs_per_bo]; memset(fpbo->slots, 0, 8 * fp->progs_per_bo); if(fp->fpbo) @@ -1225,8 +1242,8 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx) nouveau_bo_new(nvfx->screen->base.device, NOUVEAU_BO_VRAM | NOUVEAU_BO_MAP, 64, fp->prog_size * fp->progs_per_bo, &fpbo->bo); nouveau_bo_map(fpbo->bo, NOUVEAU_BO_NOSYNC); - uint8_t* map = fpbo->bo->map; - uint8_t* buf = (uint8_t*)fpbo->insn; + map = fpbo->bo->map; + buf = (uint8_t*)fpbo->insn; for(unsigned i = 0; i < fp->progs_per_bo; ++i) { memcpy(buf, fp->insn, fp->insn_len * 4); @@ -1238,8 +1255,8 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx) fp->bo_prog_idx = 0; } - int offset = fp->bo_prog_idx * fp->prog_size; - uint32_t* fpmap = (uint32_t*)((char*)fp->fpbo->bo->map + offset); + offset = fp->bo_prog_idx * fp->prog_size; + fpmap = (uint32_t*)((char*)fp->fpbo->bo->map + offset); if(nvfx->constbuf[PIPE_SHADER_FRAGMENT]) { struct pipe_resource* constbuf = nvfx->constbuf[PIPE_SHADER_FRAGMENT]; diff --git a/src/gallium/drivers/nvfx/nvfx_miptree.c b/src/gallium/drivers/nvfx/nvfx_miptree.c index 559e832109d..0532b43ef03 100644 --- a/src/gallium/drivers/nvfx/nvfx_miptree.c +++ b/src/gallium/drivers/nvfx/nvfx_miptree.c @@ -155,9 +155,10 @@ struct pipe_resource * nvfx_miptree_create(struct pipe_screen *pscreen, const struct pipe_resource *pt) { struct nvfx_miptree* mt = nvfx_miptree_create_skeleton(pscreen, pt); + unsigned size; nvfx_miptree_choose_format(mt); - unsigned size = nvfx_miptree_layout(mt); + size = nvfx_miptree_layout(mt); mt->base.bo = nouveau_screen_bo_new(pscreen, 256, pt->usage, pt->bind, size); @@ -173,6 +174,7 @@ struct pipe_resource * nvfx_miptree_from_handle(struct pipe_screen *pscreen, const struct pipe_resource *template, struct winsys_handle *whandle) { struct nvfx_miptree* mt = nvfx_miptree_create_skeleton(pscreen, template); + unsigned stride; if(whandle->stride) { mt->linear_pitch = whandle->stride; mt->base.base.flags |= NVFX_RESOURCE_FLAG_LINEAR; @@ -181,7 +183,6 @@ nvfx_miptree_from_handle(struct pipe_screen *pscreen, const struct pipe_resource nvfx_miptree_layout(mt); - unsigned stride; mt->base.bo = nouveau_screen_bo_from_handle(pscreen, whandle, &stride); if (mt->base.bo == NULL) { FREE(mt); diff --git a/src/gallium/drivers/nvfx/nvfx_state_emit.c b/src/gallium/drivers/nvfx/nvfx_state_emit.c index 19512194be6..8e3c342179d 100644 --- a/src/gallium/drivers/nvfx/nvfx_state_emit.c +++ b/src/gallium/drivers/nvfx/nvfx_state_emit.c @@ -11,6 +11,7 @@ nvfx_state_validate_common(struct nvfx_context *nvfx) unsigned still_dirty = 0; int all_swizzled = -1; boolean flush_tex_cache = FALSE; + unsigned render_temps; if(nvfx != nvfx->screen->cur_ctx) { @@ -141,7 +142,7 @@ nvfx_state_validate_common(struct nvfx_context *nvfx) nvfx->dirty = dirty & still_dirty; - unsigned render_temps = nvfx->state.render_temps; + render_temps = nvfx->state.render_temps; if(render_temps) { for(int i = 0; i < nvfx->framebuffer.nr_cbufs; ++i) diff --git a/src/gallium/drivers/nvfx/nvfx_surface.c b/src/gallium/drivers/nvfx/nvfx_surface.c index 135978ad274..806f1a22e65 100644 --- a/src/gallium/drivers/nvfx/nvfx_surface.c +++ b/src/gallium/drivers/nvfx/nvfx_surface.c @@ -60,14 +60,17 @@ nvfx_region_set_format(struct nv04_region* rgn, enum pipe_format format) rgn->bpps = 2; break; default: - assert(util_is_pot(bits)); - int shift = util_logbase2(bits) - 3; - assert(shift >= 2); - rgn->bpps = 2; - shift -= 2; - - rgn->x = util_format_get_nblocksx(format, rgn->x) << shift; - rgn->y = util_format_get_nblocksy(format, rgn->y); + { + int shift; + assert(util_is_pot(bits)); + shift = util_logbase2(bits) - 3; + assert(shift >= 2); + rgn->bpps = 2; + shift -= 2; + + rgn->x = util_format_get_nblocksx(format, rgn->x) << shift; + rgn->y = util_format_get_nblocksy(format, rgn->y); + } } } @@ -241,26 +244,29 @@ nvfx_resource_copy_region(struct pipe_context *pipe, unsigned srcx, unsigned srcy, unsigned srcz, unsigned w, unsigned h) { + static int copy_threshold = -1; struct nv04_2d_context *ctx = nvfx_screen(pipe->screen)->eng2d; struct nv04_region dst, src; + int dst_to_gpu; + int src_on_gpu; + boolean small; + int ret; if(!w || !h) return; - static int copy_threshold = -1; if(copy_threshold < 0) copy_threshold = debug_get_num_option("NOUVEAU_COPY_THRESHOLD", 4); - int dst_to_gpu = dstr->usage != PIPE_USAGE_DYNAMIC && dstr->usage != PIPE_USAGE_STAGING; - int src_on_gpu = nvfx_resource_on_gpu(srcr); + dst_to_gpu = dstr->usage != PIPE_USAGE_DYNAMIC && dstr->usage != PIPE_USAGE_STAGING; + src_on_gpu = nvfx_resource_on_gpu(srcr); nvfx_region_init_for_subresource(&dst, dstr, subdst, dstx, dsty, dstz, TRUE); nvfx_region_init_for_subresource(&src, srcr, subsrc, srcx, srcy, srcz, FALSE); w = util_format_get_stride(dstr->format, w) >> dst.bpps; h = util_format_get_nblocksy(dstr->format, h); - int ret; - boolean small = (w * h <= copy_threshold); + small = (w * h <= copy_threshold); if((!dst_to_gpu || !src_on_gpu) && small) ret = -1; /* use the CPU */ else @@ -309,6 +315,7 @@ nvfx_surface_fill(struct pipe_context* pipe, struct pipe_surface *dsts, { struct nv04_2d_context *ctx = nvfx_screen(pipe->screen)->eng2d; struct nv04_region dst; + int ret; /* Always try to use the GPU right now, if possible * If the user wanted the surface data on the CPU, he would have cleared with memset (hopefully) */ @@ -318,7 +325,7 @@ nvfx_surface_fill(struct pipe_context* pipe, struct pipe_surface *dsts, w = util_format_get_stride(dsts->format, w) >> dst.bpps; h = util_format_get_nblocksy(dsts->format, h); - int ret = nv04_region_fill_2d(ctx, &dst, w, h, value); + ret = nv04_region_fill_2d(ctx, &dst, w, h, value); if(ret > 0 && dsts->texture->bind & PIPE_BIND_RENDER_TARGET) return 1; else if(ret) diff --git a/src/gallium/drivers/nvfx/nvfx_vbo.c b/src/gallium/drivers/nvfx/nvfx_vbo.c index d1e71992875..5d3fb6fb6cb 100644 --- a/src/gallium/drivers/nvfx/nvfx_vbo.c +++ b/src/gallium/drivers/nvfx/nvfx_vbo.c @@ -58,6 +58,10 @@ static unsigned nvfx_decide_upload_mode(struct pipe_context *pipe, const struct unsigned inline_cost = 0; unsigned unique_vertices; unsigned upload_mode; + float best_index_cost_for_hardware_vertices_as_inline_cost; + boolean prefer_hardware_indices; + unsigned index_inline_cost; + unsigned index_hardware_cost; if (info->indexed) unique_vertices = util_guess_unique_indices_count(info->mode, info->count); else @@ -108,10 +112,10 @@ static unsigned nvfx_decide_upload_mode(struct pipe_context *pipe, const struct inline_cost += vbi->per_vertex_size * info->count; } - float best_index_cost_for_hardware_vertices_as_inline_cost = 0.0f; - boolean prefer_hardware_indices = FALSE; - unsigned index_inline_cost = 0; - unsigned index_hardware_cost = 0; + best_index_cost_for_hardware_vertices_as_inline_cost = 0.0f; + prefer_hardware_indices = FALSE; + index_inline_cost = 0; + index_hardware_cost = 0; if (info->indexed) { @@ -336,12 +340,15 @@ nvfx_vbo_validate(struct nvfx_context *nvfx) void nvfx_vbo_relocate(struct nvfx_context *nvfx) { + struct nouveau_channel* chan; + unsigned vb_flags; + int i; + if(!nvfx->use_vertex_buffers) return; - struct nouveau_channel* chan = nvfx->screen->base.channel; - unsigned vb_flags = nvfx->screen->vertex_buffer_reloc_flags | NOUVEAU_BO_RD | NOUVEAU_BO_DUMMY; - int i; + chan = nvfx->screen->base.channel; + vb_flags = nvfx->screen->vertex_buffer_reloc_flags | NOUVEAU_BO_RD | NOUVEAU_BO_DUMMY; MARK_RING(chan, 2 * 16 + 3, 2 * 16 + 3); for (i = 0; i < nvfx->vtxelt->num_per_vertex; i++) { @@ -422,10 +429,10 @@ nvfx_vtxelts_state_create(struct pipe_context *pipe, struct nvfx_vtxelt_state *cso = CALLOC_STRUCT(nvfx_vtxelt_state); struct translate_key transkey; unsigned per_vertex_size[16]; - memset(per_vertex_size, 0, sizeof(per_vertex_size)); - unsigned vb_compacted_index[16]; + memset(per_vertex_size, 0, sizeof(per_vertex_size)); + assert(num_elements < 16); /* not doing fallbacks yet */ memcpy(cso->pipe, elements, num_elements * sizeof(elements[0]));