From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 26 Sep 2020 23:31:30 +0000 (+0100)
Subject: DMI-to-JTAG needed to be "sync" to get ack/resp right
X-Git-Tag: 24jan2021_ls180~304
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=48ae7f9edd24244586aafcc28779209042af3a24;p=soc.git

DMI-to-JTAG needed to be "sync" to get ack/resp right
---

diff --git a/src/soc/litex/florent/idcode_test2.svf b/src/soc/litex/florent/idcode_test2.svf
index c1498cf8..e83d8851 100644
--- a/src/soc/litex/florent/idcode_test2.svf
+++ b/src/soc/litex/florent/idcode_test2.svf
@@ -15,5 +15,14 @@ SDR 8 TDI (2) SMASK (ff) ;
 // set to DMI "data read"
 SIR 4 TDI (9) SMASK (f) ;
 // read 64 bit
+SDR 64 TDI (0000000000000000) SMASK (0000000000000000) TDO (00000000deadbeef) MASK (0000000000000000) ;
+
+// set to DMI "address"
+SIR 4 TDI (8) SMASK (f) ;
+// set DMI "CR" address (8)
+SDR 8 TDI (8) SMASK (ff) ;
+// set to DMI "data read"
+SIR 4 TDI (9) SMASK (f) ;
+// read 64 bit
 SDR 64 TDI (0000000000000000) SMASK (0000000000000000) TDO (00000000deadbeef) MASK (ffffffffffffffff) ;
 
diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 4582e4ec..73f69b5f 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -119,7 +119,7 @@ class TestIssuer(Elaboratable):
             m.submodules.jtag = jtag = self.jtag
             # TODO: UART2GDB mux, here, from external pin
             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
-            comb += dbg.dmi.connect_to(jtag.dmi)
+            sync += dbg.dmi.connect_to(jtag.dmi)
 
         cur_state = self.cur_state