From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 20 Feb 2020 17:27:10 +0000 (+0000)
Subject: move part_sig_add name
X-Git-Tag: partial-core-ls180-gdsii~234
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=48b0d3dd880714ffd67c59518a673f7eb9dbdd99;p=soclayout.git

move part_sig_add name
---

diff --git a/examples/part_sig_add.py b/examples/part_sig_add.py
index 5a868b4..0113e04 100644
--- a/examples/part_sig_add.py
+++ b/examples/part_sig_add.py
@@ -14,15 +14,15 @@ def test():
                                 module.b.sig,
                                 module.add_output,
                                 module.eq_output],
-                               "top")
+                               "part_sig_add")
                             
 def run_yosys(test_name):
     liberty_file = os.getenv("HOME")+"/coriolis-2.x/src/alliance-check-toolkit/cells/nsxlib/nsxlib.lib"
     print("test_name:",test_name)
     cmd = [
-        "read_ilang top.il",
-        "hierarchy -check -top top",
-        "synth -top top",
+        "read_ilang part_sig_add.il",
+        "hierarchy -check -top part_sig_add",
+        "synth -top part_sig_add",
         "dfflibmap -liberty "+liberty_file,
         "abc -liberty "+liberty_file,
         "clean",
@@ -35,7 +35,7 @@ def create_ilang(dut, ports, test_name):
     vl = rtlil.convert(dut, name=test_name, ports=ports)
     with open("%s.il" % test_name, "w") as f:
         f.write(vl)
-    run_yosys(test_name)
+    #run_yosys(test_name)
 
 
 if __name__ == "__main__":