From: lkcl Date: Mon, 16 May 2022 12:23:57 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~2201 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=48b19624d8fe5a8343a26950ec69258d1fa066f3;p=libreriscv.git --- diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn index 33182ed5f..cb0ac3f1f 100644 --- a/openpower/sv/bitmanip.mdwn +++ b/openpower/sv/bitmanip.mdwn @@ -41,8 +41,8 @@ two major opcodes are needed ternlog has its own major opcode -| 29.30 |31| name | -| ------ |--| --------- | +| 29.30 |31| name | Form | +| ------ |--| --------- | ---- | | 0 0 |Rc| ternlogi | TLI-Form | | 0 1 | | crternlogi | TLI-Form | | 1 iv | | grevlogi | TLI-Form | @@ -52,7 +52,7 @@ ternlog has its own major opcode | 28.30 |31| name | | ------ |--| --------- | | -00 |0 | xpermi | -| -00 |1 | rsvd | +| -00 |1 | binary lut | | -01 |0 | grevlog | | -01 |1 | grevlogw | | 010 |Rc| bitmask | @@ -94,15 +94,15 @@ TODO: convert all instructions to use RT and not RS | 0.5|6.10|11.15|16.20 |21..25 | 26....30 |31| name | Form | | -- | -- | --- | --- | ----- | -------- |--| ------ | -------- | -| NN | RT | RA |itype/| im0-4 | im5-7 00 |0 | xpermi | | +| NN | RT | RA |itype/| im0-4 | im5-7 00 |0 | xpermi | TLI-Form | | NN | RT | RA | RB | RC | nh 00 00 |1 | binlut | | | NN | RT | RA | RB | BFC// | 0 01 00 |1 | bincrflut | | | NN | | | | | 1 01 00 |1 | rsvd | | | NN | | | | | - 10 00 |1 | rsvd | | | NN | | | | | 0 11 00 |1 | svshape | | | NN | | | | | 1 11 00 |1 | svstep | | -| NN | RT | RA | RB | im0-4 | im5-7 01 |0 | grevlog | | -| NN | RT | RA | RB | im0-4 | im5-7 01 |1 | grevlogw | | +| NN | RT | RA | RB | im0-4 | im5-7 01 |0 | grevlog | TLI-Form | +| NN | RT | RA | RB | im0-4 | im5-7 01 |1 | grevlogw | TLI-Form | | NN | RT | RA | RB | RC | mode 010 |Rc| bitmask\* | | | NN | | | | | 0- 011 | | rsvd | | | NN | | | | | 10 011 |Rc| svstep | |