From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 29 Jun 2020 08:33:39 +0000 (+0200)
Subject: sim - error when memrd and memwr detected
X-Git-Tag: working-ls180~436^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=48b6d3272c3f6ebf1ee1aab3a8abeb5017519b82;p=yosys.git

sim - error when memrd and memwr detected
---

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 1ab082b09..fb496ff87 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -163,7 +163,10 @@ struct SimInstance
 
 				mem_database[cell] = mem;
 			}
-
+			if (cell->type.in(ID($memwr),ID($memrd)))
+			{
+				log_error("$memrd and $memwr cells have to be merged to stand-alone $mem cells (execute memory_collect pass)\n");
+			}
 			if (cell->type.in(ID($assert), ID($cover), ID($assume))) {
 				formal_database.insert(cell);
 			}