From: Luke Kenneth Casson Leighton Date: Thu, 23 Dec 2021 20:04:54 +0000 (+0000) Subject: somehow managed to miss out setting r1.forward_valid1 in dcache X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=48c6378092f088fd532ef36fed9dc347899c4605;p=soc.git somehow managed to miss out setting r1.forward_valid1 in dcache --- diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index f63ed521..3bfe772f 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -1529,6 +1529,7 @@ class DCache(Elaboratable): sync += r1.wb.adr[:LINE_OFF_BITS-ROW_OFF_BITS].eq(row+1) # Incoming acks processing + sync += r1.forward_valid1.eq(bus.ack) with m.If(bus.ack): srow = Signal(ROW_LINE_BITS) comb += srow.eq(r1.store_row)