From: lkcl <lkcl@web>
Date: Sat, 4 Jun 2022 21:47:22 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1963
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=48d000a397f22463d03cdd4f7d91992c79316a39;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index e16f700f8..f7117b08e 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -49,6 +49,16 @@ Advantages of these design principles:
   but off of Vectorisation ISAs as well.  No more separate Vector
   instructions.
 
+Comparative instruction count:
+
+* ARM NEON SIMD: around 2,000 instructions, prerequisite: ARM Scalar.
+* ARM SVE: around 4,000 instructions, prerequisite: NEON. 
+* ARM SVE2: around 1,000 instructions, prerequisite: SVE
+* Intel AVX-512: around 4,000 instructions, prerequisite AVX2 etc.
+* RISV-V RVV: 192 instructions, prerequisite 96 Scalar RV64GC instructions
+* SVP64: **four** instructions, prerequisite SFS (150) or
+  SFFS (214) Compliancy Subsets
+
 # Major opcodes summary
 
 Please be advised that even though below is entirely DRAFT status, there