From: Kaj Tuomi Date: Sat, 18 May 2019 11:20:30 +0000 (+0300) Subject: Read bigger Verilog files. X-Git-Tag: yosys-0.9~118^2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=48ddbe52fb1428fc8f7f3d6444c5637eb151475f;p=yosys.git Read bigger Verilog files. Hit parser limit with 3M gate design. This commit fix it. --- diff --git a/frontends/verilog/Makefile.inc b/frontends/verilog/Makefile.inc index 0a1f97ac0..6a8462b41 100644 --- a/frontends/verilog/Makefile.inc +++ b/frontends/verilog/Makefile.inc @@ -14,7 +14,7 @@ frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l $(Q) mkdir -p $(dir $@) $(P) flex -o frontends/verilog/verilog_lexer.cc $< -frontends/verilog/verilog_parser.tab.o: CXXFLAGS += -DYYMAXDEPTH=100000 +frontends/verilog/verilog_parser.tab.o: CXXFLAGS += -DYYMAXDEPTH=10000000 OBJS += frontends/verilog/verilog_parser.tab.o OBJS += frontends/verilog/verilog_lexer.o