From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Thu, 26 Sep 2019 00:53:55 +0000 (+1000)
Subject: Multiply needs to be 16 stages to fix all timing issues
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=48e6e719d302b0484c608a51788a02fca0c2ce43;p=microwatt.git

Multiply needs to be 16 stages to fix all timing issues

This seems dependent on the FPGA type/size, so we should probably
make it a toplevel generic, but for now this helps on the
Arty A7-35

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---

diff --git a/multiply.vhdl b/multiply.vhdl
index 6f80660..71aceca 100644
--- a/multiply.vhdl
+++ b/multiply.vhdl
@@ -10,7 +10,7 @@ use work.crhelpers.all;
 
 entity multiply is
     generic (
-        PIPELINE_DEPTH : natural := 2
+        PIPELINE_DEPTH : natural := 16
         );
     port (
         clk   : in std_logic;