From: Rob Clark <robdclark@gmail.com>
Date: Sun, 3 Dec 2017 16:48:56 +0000 (-0500)
Subject: freedreno/ir3: all mem instructions have WAR hazzard
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=48eef0c18248db948378ecf9a5f9930fa467ae9f;p=mesa.git

freedreno/ir3: all mem instructions have WAR hazzard

It isn't just load instructions that have write-after-read hazzard.

Fixes stk gaussian blur compute shaders.

Signed-off-by: Rob Clark <robdclark@gmail.com>
---

diff --git a/src/gallium/drivers/freedreno/ir3/ir3_legalize.c b/src/gallium/drivers/freedreno/ir3/ir3_legalize.c
index 3f12b68ada1..b4d5db58ccb 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_legalize.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_legalize.c
@@ -211,7 +211,7 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
 		/* both tex/sfu appear to not always immediately consume
 		 * their src register(s):
 		 */
-		if (is_tex(n) || is_sfu(n) || is_load(n)) {
+		if (is_tex(n) || is_sfu(n) || is_mem(n)) {
 			foreach_src(reg, n) {
 				if (reg_gpr(reg))
 					regmask_set(&needs_ss_war, reg);