From: lkcl <lkcl@web>
Date: Mon, 27 Jun 2022 11:28:00 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1495
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=49413c05f79eb0d9da1252d3d20c7a3cd2d66d05;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index d1c5d76a9..534d91362 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -397,7 +397,7 @@ With EXTRA2 restricting starting points
 to multiples of 8 (CR0, CR8, CR16...) both Vectorised Rc=1 and CR Predicate
 Masks have to be adapted to fit on these boundaries as well.
 
-# Extra Remapped Encoding
+# Extra Remapped Encoding <a name="extra_remap"> </a>
 
 Shows all instruction-specific fields in the Remapped Encoding `RM[10:18]` for all instruction variants.  Note that due to the very tight space, the encoding mode is *not* included in the prefix itself.  The mode is "applied", similar to OpenPOWER "Forms" (X-Form, D-Form) on a per-instruction basis, and, like "Forms" are given a designation (below) of the form `RM-nP-nSnD`. The full list of which instructions use which remaps is here [[opcode_regs_deduped]]. (*Machine-readable CSV files have been provided which will make the task of creating SV-aware ISA decoders easier*).