From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 21 Oct 2021 12:06:35 +0000 (+0100)
Subject: found an error in PartitionedAssign and PartitionedRepl
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=494757caa1f89c14df8ea83ed9f1e450b2c0b0d4;p=ieee754fpu.git

found an error in PartitionedAssign and PartitionedRepl
where Slice was accidentally being done on SimdSignal rather than
SimdSignals internal sig.  whilst this was a legitimate oversight
the bug should have been found when a NotImplemented SimdSignal.__Slice__
was added.

Project Development Practices were violated here by unit tests not
having been run, which would have easily detected the bug
---

diff --git a/src/ieee754/part_ass/assign.py b/src/ieee754/part_ass/assign.py
index 2a79cbbc..81873bcb 100644
--- a/src/ieee754/part_ass/assign.py
+++ b/src/ieee754/part_ass/assign.py
@@ -71,7 +71,8 @@ class PartitionedAssign(Elaboratable):
         start = keys[upto]
         end = keys[upto+numparts]
         print ("start end", start, end, len(x))
-        return x[start:end]
+        # access the underlying signal of SimdSignal directly
+        return x.sig[start:end]
 
     def elaborate(self, platform):
         m = Module()
diff --git a/src/ieee754/part_repl/repl.py b/src/ieee754/part_repl/repl.py
index 73476483..05db372a 100644
--- a/src/ieee754/part_repl/repl.py
+++ b/src/ieee754/part_repl/repl.py
@@ -73,7 +73,8 @@ class PartitionedRepl(Elaboratable):
         start = keys[upto]
         end = keys[upto+numparts]
         print ("start end", start, end, len(x))
-        return x[start:end]
+        # access the underlying Signal of SimdSignal directly
+        return x.sig[start:end]
 
     def elaborate(self, platform):
         m = Module()