From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 21 Jun 2007 20:35:25 +0000 (+0000)
Subject: Merge zizzer.eecs.umich.edu:/bk/newmem
X-Git-Tag: m5_2.0_beta4~311
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=49490b334af3bc145071a9a81f37012e7693af59;p=gem5.git

Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-micro

src/cpu/o3/fetch_impl.hh:
    hand merge

--HG--
extra : convert_revision : 3f71f3ac2035eec8b6f7bceb6906edb4dd09c045
---

49490b334af3bc145071a9a81f37012e7693af59
diff --cc src/cpu/o3/fetch_impl.hh
index 1ce5bd20f,857a08629..01e9b5b31
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@@ -1119,80 -1111,92 +1111,92 @@@ DefaultFetch<Impl>::fetch(bool &status_
              // Make sure this is a valid index.
              assert(offset <= cacheBlkSize - instSize);
  
-             // Get the instruction from the array of the cache line.
-             inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
-                         (&cacheData[tid][offset]));
+             if (!macroop) {
+                 // Get the instruction from the array of the cache line.
+                 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
+                             (&cacheData[tid][offset]));
  
-             predecoder.setTC(cpu->thread[tid]->getTC());
-             predecoder.moreBytes(fetch_PC, fetch_PC, inst);
+                 predecoder.setTC(cpu->thread[tid]->getTC());
 -                predecoder.moreBytes(fetch_PC, fetch_PC, 0, inst);
++                predecoder.moreBytes(fetch_PC, fetch_PC, inst);
  
-             ext_inst = predecoder.getExtMachInst();
+                 ext_inst = predecoder.getExtMachInst();
+                 staticInst = StaticInstPtr(ext_inst, fetch_PC);
+                 if (staticInst->isMacroop())
+                     macroop = staticInst;
+             }
+             do {
+                 if (macroop) {
+                     staticInst = macroop->fetchMicroop(fetch_MicroPC);
+                     if (staticInst->isLastMicroop())
+                         macroop = NULL;
+                 }
  
-             // Create a new DynInst from the instruction fetched.
-             DynInstPtr instruction = new DynInst(ext_inst,
-                                                  fetch_PC, fetch_NPC,
-                                                  next_PC, next_NPC,
-                                                  inst_seq, cpu);
-             instruction->setTid(tid);
+                 // Get a sequence number.
+                 inst_seq = cpu->getAndIncrementInstSeq();
  
-             instruction->setASID(tid);
+                 // Create a new DynInst from the instruction fetched.
+                 DynInstPtr instruction = new DynInst(staticInst,
+                                                      fetch_PC, fetch_NPC, fetch_MicroPC,
+                                                      next_PC, next_NPC, next_MicroPC,
+                                                      inst_seq, cpu);
+                 instruction->setTid(tid);
  
-             instruction->setThreadState(cpu->thread[tid]);
+                 instruction->setASID(tid);
  
-             DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
-                     "[sn:%lli]\n",
-                     tid, instruction->readPC(), inst_seq);
+                 instruction->setThreadState(cpu->thread[tid]);
  
-             //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst);
+                 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
+                         "[sn:%lli]\n",
+                         tid, instruction->readPC(), inst_seq);
  
-             DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
-                     tid, instruction->staticInst->disassemble(fetch_PC));
+                 //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst);
+ 
+                 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
+                         tid, instruction->staticInst->disassemble(fetch_PC));
  
  #if TRACING_ON
-             instruction->traceData =
-                 Trace::getInstRecord(curTick, cpu->tcBase(tid),
-                                      instruction->staticInst,
-                                      instruction->readPC());
+                 instruction->traceData =
+                     Trace::getInstRecord(curTick, cpu->tcBase(tid),
+                                          instruction->staticInst,
+                                          instruction->readPC());
  #else
-             instruction->traceData = NULL;
+                 instruction->traceData = NULL;
  #endif
  
-             ///FIXME This needs to be more robust in dealing with delay slots
- #if !ISA_HAS_DELAY_SLOT
- //	    predicted_branch |=
- #endif
-             lookupAndUpdateNextPC(instruction, next_PC, next_NPC);
-             predicted_branch |= (next_PC != fetch_NPC);
+                 ///FIXME This needs to be more robust in dealing with delay slots
+                 predicted_branch |=
+                     lookupAndUpdateNextPC(instruction, next_PC, next_NPC, next_MicroPC);
  
-             // Add instruction to the CPU's list of instructions.
-             instruction->setInstListIt(cpu->addInst(instruction));
+                 // Add instruction to the CPU's list of instructions.
+                 instruction->setInstListIt(cpu->addInst(instruction));
  
-             // Write the instruction to the first slot in the queue
-             // that heads to decode.
-             toDecode->insts[numInst] = instruction;
+                 // Write the instruction to the first slot in the queue
+                 // that heads to decode.
+                 toDecode->insts[numInst] = instruction;
  
-             toDecode->size++;
+                 toDecode->size++;
  
-             // Increment stat of fetched instructions.
-             ++fetchedInsts;
+                 // Increment stat of fetched instructions.
+                 ++fetchedInsts;
  
-             // Move to the next instruction, unless we have a branch.
-             fetch_PC = next_PC;
-             fetch_NPC = next_NPC;
+                 // Move to the next instruction, unless we have a branch.
+                 fetch_PC = next_PC;
+                 fetch_NPC = next_NPC;
+                 fetch_MicroPC = next_MicroPC;
  
-             if (instruction->isQuiesce()) {
-                 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
-                         curTick);
-                 fetchStatus[tid] = QuiescePending;
-                 ++numInst;
-                 status_change = true;
-                 break;
-             }
+                 if (instruction->isQuiesce()) {
+                     DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
+                             curTick);
+                     fetchStatus[tid] = QuiescePending;
+                     ++numInst;
+                     status_change = true;
+                     break;
+                 }
  
+                 ++numInst;
+             } while (staticInst->isMicroop() &&
+                      !staticInst->isLastMicroop() &&
+                      numInst < fetchWidth);
              offset += instSize;
          }