From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 5 Feb 2020 20:43:46 +0000 (+0000)
Subject: add extra tests, find out whats going on with eq_gt_ge
X-Git-Tag: ls180-24jan2020~264
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=494caee3f35c6ac825f84818ec2eb7bf5586c0b4;p=ieee754fpu.git

add extra tests, find out whats going on with eq_gt_ge
---

diff --git a/src/ieee754/part_cmp/eq_gt_ge.py b/src/ieee754/part_cmp/eq_gt_ge.py
index d010c21b..7120ca1f 100644
--- a/src/ieee754/part_cmp/eq_gt_ge.py
+++ b/src/ieee754/part_cmp/eq_gt_ge.py
@@ -107,13 +107,17 @@ if __name__ == "__main__":
     sim = Simulator(m)
 
     def process():
-        yield mask.eq(0b10)
+        yield mask.eq(0b010)
         yield egg.a.eq(0xf000)
         yield egg.b.eq(0)
         yield Delay(1e-6)
         out = yield egg.output
         print ("out", bin(out))
-        yield mask.eq(0b1111)
+        yield mask.eq(0b111)
+        yield egg.a.eq(0x0000)
+        yield egg.b.eq(0)
+        yield Delay(1e-6)
+        yield mask.eq(0b010)
         yield egg.a.eq(0x0000)
         yield egg.b.eq(0)
         yield Delay(1e-6)