From: Claire Xen <claire@clairexen.net>
Date: Fri, 11 Feb 2022 15:03:12 +0000 (+0100)
Subject: Merge branch 'master' into clk2ff-better-names
X-Git-Tag: yosys-0.15~27^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=49545c73f7f5a5cf73d287fd371f2ff39311f621;p=yosys.git

Merge branch 'master' into clk2ff-better-names
---

49545c73f7f5a5cf73d287fd371f2ff39311f621
diff --cc passes/sat/clk2fflogic.cc
index b9ba5ee3c,a292941c8..f37e07a89
--- a/passes/sat/clk2fflogic.cc
+++ b/passes/sat/clk2fflogic.cc
@@@ -156,13 -153,24 +156,31 @@@ struct Clk2fflogicPass : public Pass 
  						continue;
  					}
  
+ 					if (ff.has_clk) {
+ 						log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n",
+ 								log_id(module), log_id(cell), log_id(cell->type),
+ 								log_signal(ff.sig_clk), log_signal(ff.sig_d), log_signal(ff.sig_q));
+ 					} else if (ff.has_aload) {
+ 						log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
+ 								log_id(module), log_id(cell), log_id(cell->type),
+ 								log_signal(ff.sig_aload), log_signal(ff.sig_ad), log_signal(ff.sig_q));
+ 					} else {
+ 						// $sr.
+ 						log("Replacing %s.%s (%s): SET=%s, CLR=%s, Q=%s\n",
+ 								log_id(module), log_id(cell), log_id(cell->type),
+ 								log_signal(ff.sig_set), log_signal(ff.sig_clr), log_signal(ff.sig_q));
+ 					}
+ 
+ 					ff.remove();
+ 
 -					Wire *past_q = module->addWire(NEW_ID, ff.width);
 +					// Strip spaces from signal name, since Yosys IDs can't contain spaces
- 					// Spaces only occur when have a signal that's a slice of a larger bus,
++					// Spaces only occur when we have a signal that's a slice of a larger bus,
 +					// e.g. "\myreg [5:0]", so removing spaces shouldn't result in loss of uniqueness
 +					std::string sig_q_str = log_signal(ff.sig_q);
 +					sig_q_str.erase(std::remove(sig_q_str.begin(), sig_q_str.end(), ' '), sig_q_str.end());
 +
 +					Wire *past_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#past_q_wire", sig_q_str.c_str())), ff.width);
++          
  					if (!ff.is_fine) {
  						module->addFf(NEW_ID, ff.sig_q, past_q);
  					} else {
@@@ -172,9 -180,9 +190,9 @@@
  						initvals.set_init(past_q, ff.val_init);
  
  					if (ff.has_clk) {
- 						ff.unmap_ce_srst(module);
+ 						ff.unmap_ce_srst();
  
 -						Wire *past_clk = module->addWire(NEW_ID);
 +						Wire *past_clk = module->addWire(NEW_ID_SUFFIX(stringf("%s#past_clk#%s", sig_q_str.c_str(), log_signal(ff.sig_clk))));
  						initvals.set_init(past_clk, ff.pol_clk ? State::S1 : State::S0);
  
  						if (!ff.is_fine)