From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Sun, 1 Feb 2015 20:49:55 +0000 (+0100)
Subject: Fixed typos found by lintian
X-Git-Tag: yosys-0.5~33^2^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=49649d6ef06f87d913d7b9ddd9e1aee0ecb3a961;p=yosys.git

Fixed typos found by lintian
---

diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index 16b66d47d..69da710f2 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -1174,7 +1174,7 @@ struct AbcPass : public Pass {
 		log("    -markgroups\n");
 		log("        set a 'abcgroup' attribute on all objects created by ABC. The value of\n");
 		log("        this attribute is a unique integer for each ABC process started. This\n");
-		log("        is usefull for debugging the partitioning of clock domains.\n");
+		log("        is useful for debugging the partitioning of clock domains.\n");
 		log("\n");
 		log("When neither -liberty nor -lut is used, the Yosys standard cell library is\n");
 		log("loaded into ABC before the ABC script is executed.\n");
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index 954c2ff7c..8f4214027 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -1110,7 +1110,7 @@ struct MemoryBramPass : public Pass {
 		log("It is possible to match against the following values with min/max rules:\n");
 		log("\n");
 		log("    words  ........  number of words in memory in design\n");
-		log("    abits  ........  number of adress bits on memory in design\n");
+		log("    abits  ........  number of address bits on memory in design\n");
 		log("    dbits  ........  number of data bits on memory in design\n");
 		log("    wports  .......  number of write ports on memory in design\n");
 		log("    rports  .......  number of read ports on memory in design\n");
@@ -1137,7 +1137,7 @@ struct MemoryBramPass : public Pass {
 		log("the next also has 'or_next_if_better' set, and so forth).\n");
 		log("\n");
 		log("A match containing the command 'make_transp' will add external circuitry\n");
-		log("to simulate 'transparent read', if neccessary.\n");
+		log("to simulate 'transparent read', if necessary.\n");
 		log("\n");
 		log("A match containing the command 'shuffle_enable A' will re-organize\n");
 		log("the data bits to accommodate the enable pattern of port A.\n");