From: Ali Saidi Date: Tue, 18 May 2004 20:26:16 +0000 (-0400) Subject: Major clean up of alpha system files. X-Git-Tag: stable_2012_02_02~553^2~2^2~32 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=496c48d9b2cdf77e7c73c04307db9a0ff19828c0;p=gem5.git Major clean up of alpha system files. console/Makefile: palcode/Makefile: moved header files to /h so updated make file for that console/dbmentry.s: console/paljtokern.s: console/paljtoslave.s: upadated to use osf file that the palcode uses, one less file --- diff --git a/system/alpha/console/Makefile b/system/alpha/console/Makefile index 518596058..1020bfb39 100644 --- a/system/alpha/console/Makefile +++ b/system/alpha/console/Makefile @@ -33,11 +33,11 @@ printf.o: printf.c $(CC) -g3 $(INCLUDES) -nostdinc++ -o $*.o -c $*.c paljtokern.s.o: paljtokern.s - g++ -I ../palcode -E -P -nostdinc -nostdinc++ -x c++ paljtokern.s | \ + g++ -I ../h -E -P -nostdinc -nostdinc++ -x c++ paljtokern.s | \ $(AS) -m 21164 -o paljtokern.s.o paljtoslave.s.o: paljtoslave.s - g++ -I ../palcode -E -P -nostdinc -nostdinc++ -x c++ paljtoslave.s | \ + g++ -I ../h -E -P -nostdinc -nostdinc++ -x c++ paljtoslave.s | \ $(AS) -m 21164 -o paljtoslave.s.o console: console.o dbmentry.o printf.o paljtokern.s.o paljtoslave.s.o diff --git a/system/alpha/console/dbmentry.s b/system/alpha/console/dbmentry.s index 754fee234..d8741e658 100644 --- a/system/alpha/console/dbmentry.s +++ b/system/alpha/console/dbmentry.s @@ -15,7 +15,7 @@ #ifndef MAKEDEPEND #include "ev5_impure.h" #include "cserve.h" -#include "osf.h" +#include "fromHudsonOsf.h" #endif //#include "paldefs.h" diff --git a/system/alpha/console/paljtokern.s b/system/alpha/console/paljtokern.s index 979d719a9..66b593461 100644 --- a/system/alpha/console/paljtokern.s +++ b/system/alpha/console/paljtokern.s @@ -1,6 +1,7 @@ -#include "dc21164.h" // DECchip 21164 specific definitions -#include "osf.h" // OSF/1 specific definitions -#include "macros.h" // Global macro definitions +#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions +#include "ev5_defs.h" +#include "fromHudsonOsf.h" // OSF/1 specific definitions +#include "fromHudsonMacros.h" // Global macro definitions #include "ev5_impure.h" // Scratch & logout area data structures #include "platform.h" // Platform specific definitions diff --git a/system/alpha/console/paljtoslave.s b/system/alpha/console/paljtoslave.s index c1809afb7..3c3abd01c 100644 --- a/system/alpha/console/paljtoslave.s +++ b/system/alpha/console/paljtoslave.s @@ -1,6 +1,7 @@ -#include "dc21164.h" // DECchip 21164 specific definitions -#include "osf.h" // OSF/1 specific definitions -#include "macros.h" // Global macro definitions +#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions +#include "ev5_defs.h" +#include "fromHudsonOsf.h" // OSF/1 specific definitions +#include "fromHudsonMacros.h" // Global macro definitions #include "ev5_impure.h" // Scratch & logout area data structures #include "platform.h" // Platform specific definitions diff --git a/system/alpha/h/cserve.h b/system/alpha/h/cserve.h new file mode 100644 index 000000000..47a30a0a3 --- /dev/null +++ b/system/alpha/h/cserve.h @@ -0,0 +1,107 @@ +/* + * VID: [T1.2] PT: [Fri Apr 21 16:47:20 1995] SF: [cserve.h] + * TI: [/sae_users/cruz/bin/vice -iplatform.s -l// -p# -DEB164 -h -m -aeb164 ] + */ +#define __CSERVE_LOADED 1 +/* +***************************************************************************** +** * +** Copyright © 1993, 1994 * +** by Digital Equipment Corporation, Maynard, Massachusetts. * +** * +** All Rights Reserved * +** * +** Permission is hereby granted to use, copy, modify and distribute * +** this software and its documentation, in both source code and * +** object code form, and without fee, for the purpose of distribution * +** of this software or modifications of this software within products * +** incorporating an integrated circuit implementing Digital's AXP * +** architecture, regardless of the source of such integrated circuit, * +** provided that the above copyright notice and this permission notice * +** appear in all copies, and that the name of Digital Equipment * +** Corporation not be used in advertising or publicity pertaining to * +** distribution of the document or software without specific, written * +** prior permission. * +** * +** Digital Equipment Corporation disclaims all warranties and/or * +** guarantees with regard to this software, including all implied * +** warranties of fitness for a particular purpose and merchantability, * +** and makes no representations regarding the use of, or the results * +** of the use of, the software and documentation in terms of correctness, * +** accuracy, reliability, currentness or otherwise; and you rely on * +** the software, documentation and results solely at your own risk. * +** * +** AXP is a trademark of Digital Equipment Corporation. * +** * +***************************************************************************** +** +** FACILITY: +** +** DECchip 21164 OSF/1 PALcode +** +** MODULE: +** +** cserve.h +** +** MODULE DESCRIPTION: +** +** Platform specific cserve definitions. +** +** AUTHOR: ES +** +** CREATION DATE: 21-JUN-1994 +** +** $Id: cserve.h,v 1.1.1.1 1997/10/30 23:27:18 verghese Exp $ +** +** MODIFICATION HISTORY: +** +** $Log: cserve.h,v $ +** Revision 1.1.1.1 1997/10/30 23:27:18 verghese +** current 10/29/97 +** +** Revision 1.6 1995/04/03 17:29:52 samberg +** Add rd_bccfg_off +** +** Revision 1.5 1995/02/02 19:31:34 samberg +** Added WR_BCACHE, deleted WR_BCCFG and WR_BCCTL +** +** Revision 1.4 1994/12/08 17:13:34 samberg +** Add CSERVE_K_WR_BCCTL and CSERVE_K_WR_BCCFG +** +** Revision 1.3 1994/11/30 15:59:30 samberg +** Use c-style comments for c compiler use +** +** Revision 1.2 1994/11/22 19:02:46 samberg +** Add constants for ev4 backward compatibility +** +** Revision 1.2 1994/11/22 19:02:46 samberg +** Add constants for ev4 backward compatibility +** +** Revision 1.1 1994/07/08 17:01:40 samberg +** Initial revision +** +** +*/ + +/* +** Console Service (cserve) sub-function codes: +*/ +#define CSERVE_K_LDQP 0x01 +#define CSERVE_K_STQP 0x02 +#define CSERVE_K_JTOPAL 0x09 +#define CSERVE_K_WR_INT 0x0A +#define CSERVE_K_RD_IMPURE 0x0B +#define CSERVE_K_PUTC 0x0F +#define CSERVE_K_WR_ICSR 0x10 +#define CSERVE_K_WR_ICCSR 0x10 /* for ev4 backwards compatibility */ +#define CSERVE_K_RD_ICSR 0x11 +#define CSERVE_K_RD_ICCSR 0x11 /* for ev4 backwards compatibility */ +#define CSERVE_K_RD_BCCTL 0x12 +#define CSERVE_K_RD_BCCFG 0x13 + +#define CSERVE_K_WR_BCACHE 0x16 + +#define CSERVE_K_RD_BCCFG_OFF 0x17 +#define CSERVE_K_JTOKERN 0x18 + + diff --git a/system/alpha/h/dc21164FromGasSources.h b/system/alpha/h/dc21164FromGasSources.h new file mode 100644 index 000000000..9b3389269 --- /dev/null +++ b/system/alpha/h/dc21164FromGasSources.h @@ -0,0 +1,965 @@ +#ifndef DC21164FROMGASSOURCES_INCLUDED +#define DC21164FROMGASSOURCES_INCLUDED 1 + +/* +***************************************************************************** +** * +** Copyright © 1993, 1994 * +** by Digital Equipment Corporation, Maynard, Massachusetts. * +** * +** All Rights Reserved * +** * +** Permission is hereby granted to use, copy, modify and distribute * +** this software and its documentation, in both source code and * +** object code form, and without fee, for the purpose of distribution * +** of this software or modifications of this software within products * +** incorporating an integrated circuit implementing Digital's AXP * +** architecture, regardless of the source of such integrated circuit, * +** provided that the above copyright notice and this permission notice * +** appear in all copies, and that the name of Digital Equipment * +** Corporation not be used in advertising or publicity pertaining to * +** distribution of the document or software without specific, written * +** prior permission. * +** * +** Digital Equipment Corporation disclaims all warranties and/or * +** guarantees with regard to this software, including all implied * +** warranties of fitness for a particular purpose and merchantability, * +** and makes no representations regarding the use of, or the results * +** of the use of, the software and documentation in terms of correctness, * +** accuracy, reliability, currentness or otherwise; and you rely on * +** the software, documentation and results solely at your own risk. * +** * +** AXP is a trademark of Digital Equipment Corporation. * +** * +***************************************************************************** +** +** FACILITY: +** +** DECchip 21164 PALcode +** +** MODULE: +** +** dc21164.h +** +** MODULE DESCRIPTION: +** +** DECchip 21164 specific definitions +** +** AUTHOR: ER +** +** CREATION DATE: 24-Nov-1993 +** +** $Id: dc21164FromGasSources.h,v 1.1.1.1 1997/10/30 23:27:19 verghese Exp $ +** +** MODIFICATION HISTORY: +** +** $Log: dc21164FromGasSources.h,v $ +** Revision 1.1.1.1 1997/10/30 23:27:19 verghese +** current 10/29/97 +** +** Revision 1.1 1995/11/18 01:45:46 boyle +** Initial revision +** +** Revision 1.15 1995/04/21 02:06:30 fdh +** Replaced C++ style comments with Standard C style comments. +** +** Revision 1.14 1995/03/20 14:55:23 samberg +** Add flushIc to make Roger Cruz's life easier. +** +** Revision 1.13 1994/12/14 15:52:48 samberg +** Add slXmit and slRcv bit definitions +** +** Revision 1.12 1994/09/07 15:43:49 samberg +** Changes for Makefile.vpp, take out OSF definition +** +** Revision 1.11 1994/07/26 17:38:35 samberg +** Changes for SD164. +** +** Revision 1.10 1994/07/08 17:02:12 samberg +** Changes to support platform specific additions +** +** Revision 1.8 1994/05/31 15:49:21 ericr +** Moved ptKdebug from pt10 to pt13; pt10 is used in MCHK flows +** +** Revision 1.7 1994/05/26 19:29:51 ericr +** Added BC_CONFIG definitions +** +** Revision 1.6 1994/05/25 14:27:25 ericr +** Added physical bit to ldq_lp and stq_cp macros +** +** Revision 1.5 1994/05/20 18:07:50 ericr +** Changed line comments to C++ style comment character +** +** Revision 1.4 1994/01/17 21:46:54 ericr +** Added floating point register definitions +** +** Revision 1.3 1994/01/03 19:31:49 ericr +** Added cache parity error status register definitions +** +** Revision 1.2 1993/12/22 20:42:35 eric +** Added ptTrap, ptMisc and flag definitions +** Added PAL shadow regsiter definitions +** +** Revision 1.1 1993/12/16 21:55:05 eric +** Initial revision +** +** +**-- +*/ + + +/* +** +** INTERNAL PROCESSOR REGISTER DEFINITIONS +** +** The internal processor register definitions below are annotated +** with one of the following symbols: +** +** RW - The register may be read and written +** RO - The register may only be read +** WO - The register may only be written +** +** For RO and WO registers, all bits and fields within the register are +** also read-only or write-only. For RW registers, each bit or field +** within the register is annotated with one of the following: +** +** RW - The bit/field may be read and written +** RO - The bit/field may be read; writes are ignored +** WO - The bit/field may be written; reads return UNPREDICTABLE +** WZ - The bit/field may be written; reads return a zero value +** W0C - The bit/field may be read; write-zero-to-clear +** W1C - The bit/field may be read; write-one-to-clear +** WA - The bit/field may be read; write-anything-to-clear +** RC - The bit/field may be read, causing state to clear; +** writes are ignored +** +*/ + + +/* +** +** Ibox IPR Definitions: +** +*/ + +// replaced by ev5_defs.h #define isr 0x100 /* RO - Interrupt Summary */ +#define itbTag 0x101 /* WO - ITB Tag */ +#define itbPte 0x102 /* RW - ITB Page Table Entry */ +#define itbAsn 0x103 /* RW - ITB Address Space Number */ +#define itbPteTemp 0x104 /* RO - ITB Page Table Entry Temporary */ +#define itbIa 0x105 /* WO - ITB Invalidate All */ +#define itbIap 0x106 /* WO - ITB Invalidate All Process */ +#define itbIs 0x107 /* WO - ITB Invalidate Single */ +// replaced by ev5_defs.h #define sirr 0x108 /* RW - Software Interrupt Request */ +// replaced by ev5_defs.h #define astrr 0x109 /* RW - Async. System Trap Request */ +// replaced by ev5_defs.h #define aster 0x10A /* RW - Async. System Trap Enable */ +#define excAddr 0x10B /* RW - Exception Address */ +#define excSum 0x10C /* RW - Exception Summary */ +#define excMask 0x10D /* RO - Exception Mask */ +#define palBase 0x10E /* RW - PAL Base */ +#define ips 0x10F /* RW - Processor Status */ +// replaced by ev5_defs.h #define ipl 0x110 /* RW - Interrupt Priority Level */ +#define intId 0x111 /* RO - Interrupt ID */ +#define iFaultVaForm 0x112 /* RO - Formatted Faulting VA */ +#define iVptBr 0x113 /* RW - I-Stream Virtual Page Table Base */ +#define hwIntClr 0x115 /* WO - Hardware Interrupt Clear */ +#define slXmit 0x116 /* WO - Serial Line Transmit */ +#define slRcv 0x117 /* RO - Serial Line Receive */ +// replaced by ev5_defs.h #define icsr 0x118 /* RW - Ibox Control/Status */ +#define icFlush 0x119 /* WO - I-Cache Flush Control */ +#define flushIc 0x119 /* WO - I-Cache Flush Control (DC21064 Symbol) */ +#define icPerr 0x11A /* RW - I-Cache Parity Error Status */ +#define PmCtr 0x11C /* RW - Performance Counter */ + +/* +** +** Ibox Control/Status Register (ICSR) Bit Summary +** +** Extent Size Name Type Function +** ------ ---- ---- ---- ------------------------------------ +** <39> 1 TST RW,0 Assert Test Status +** <38> 1 ISTA RO I-Cache BIST Status +** <37> 1 DBS RW,1 Debug Port Select +** <36> 1 FBD RW,0 Force Bad I-Cache Data Parity +** <35> 1 FBT RW,0 Force Bad I-Cache Tag Parity +** <34> 1 FMS RW,0 Force I-Cache Miss +** <33> 1 SLE RW,0 Enable Serial Line Interrupts +** <32> 1 CRDE RW,0 Enable Correctable Error Interrupts +** <30> 1 SDE RW,0 Enable PAL Shadow Registers +** <29:28> 2 SPE RW,0 Enable I-Stream Super Page Mode +** <27> 1 HWE RW,0 Enable PALRES Instrs in Kernel Mode +** <26> 1 FPE RW,0 Enable Floating Point Instructions +** <25> 1 TMD RW,0 Disable Ibox Timeout Counter +** <24> 1 TMM RW,0 Timeout Counter Mode +** +*/ + +#define ICSR_V_TST 39 +#define ICSR_M_TST (1< 1 TMT WO,1 Serial line transmit data +** +*/ + +#define SLXMIT_V_TMT 7 +#define SLXMIT_M_TMT (1< 1 RCV RO Serial line receive data +** +*/ + +#define SLRCV_V_RCV 6 +#define SLRCV_M_RCV (1< 1 TMR W1C Timeout reset error +** <12> 1 TPE W1C Tag parity error +** <11> 1 DPE W1C Data parity error +** +*/ + +#define ICPERR_V_TMR 13 +#define ICPERR_M_TMR (1< 1 IOV WA Integer overflow +** <15> 1 INE WA Inexact result +** <14> 1 UNF WA Underflow +** <13> 1 FOV WA Overflow +** <12> 1 DZE WA Division by zero +** <11> 1 INV WA Invalid operation +** <10> 1 SWC WA Software completion +** +*/ + +#define EXC_V_IOV 16 +#define EXC_M_IOV (1< 1 SLC W1C Clear Serial Line interrupt +** <32> 1 CRDC W1C Clear Correctable Read Data interrupt +** <29> 1 PC2C W1C Clear Performance Counter 2 interrupt +** <28> 1 PC1C W1C Clear Performance Counter 1 interrupt +** <27> 1 PC0C W1C Clear Performance Counter 0 interrupt +** +*/ + +#define HWINT_V_SLC 33 +#define HWINT_M_SLC (1< 1 HLT RO External Halt interrupt +** <33> 1 SLI RO Serial Line interrupt +** <32> 1 CRD RO Correctable ECC errors +** <31> 1 MCK RO System Machine Check +** <30> 1 PFL RO Power Fail +** <29> 1 PC2 RO Performance Counter 2 interrupt +** <28> 1 PC1 RO Performance Counter 1 interrupt +** <27> 1 PC0 RO Performance Counter 0 interrupt +** <23> 1 I23 RO External Hardware interrupt +** <22> 1 I22 RO External Hardware interrupt +** <21> 1 I21 RO External Hardware interrupt +** <20> 1 I20 RO External Hardware interrupt +** <19> 1 ATR RO Async. System Trap request +** <18:4> 15 SIRR RO,0 Software Interrupt request +** <3:0> 4 ASTRR RO Async. System Trap request (USEK) +** +**/ + +#define ISR_V_HLT 34 +#define ISR_M_HLT (1< 6 OPCODE RO Opcode of faulting instruction +** <10:06> 5 RA RO Ra field of faulting instruction +** <5> 1 BAD_VA RO Bad virtual address +** <4> 1 DTB_MISS RO Reference resulted in DTB miss +** <3> 1 FOW RO Fault on write +** <2> 1 FOR RO Fault on read +** <1> 1 ACV RO Access violation +** <0> 1 WR RO Reference type +** +*/ + +#define MMSTAT_V_OPC 11 +#define MMSTAT_M_OPC (0x3F< 1 DBG1 RW,0 Mbox Debug Packet Select +** <4> 1 E_BE RW,0 Ebox Big Endian mode enable +** <3> 1 DBG0 RW,0 Debug Test Select +** <2:1> 2 SP RW,0 Superpage mode enable +** <0> 1 M_BE RW,0 Mbox Big Endian mode enable +** +*/ + +#define MCSR_V_DBG1 5 +#define MCSR_M_DBG1 (1< 1 TP1 RO Dcache bank 1 tag parity error +** <4> 1 TP0 RO Dcache bank 0 tag parity error +** <3> 1 DP1 RO Dcache bank 1 data parity error +** <2> 1 DP0 RO Dcache bank 0 data parity error +** <1> 1 LOCK W1C Locks/clears bits <5:2> +** <0> 1 SEO W1C Second Dcache parity error occurred +** +*/ + +#define DCPERR_V_TP1 5 +#define DCPERR_M_TP1 (1< 1 DOA RO Hardware Dcache Disable +** <3> 1 PERR_DIS RW,0 Disable Dcache Parity Error reporting +** <2> 1 BAD_DP RW,0 Force Dcache data bad parity +** <1> 1 FHIT RW,0 Force Dcache hit +** <0> 1 ENA RW,0 Software Dcache Enable +** +*/ + +#define DC_V_DOA 4 +#define DC_M_DOA (1< 1 WB RO,0 If set, pending WB request +** <6> 1 DREAD RO,0 If set, pending D-read request +** +*/ + +#define MAF_V_WB_PENDING 7 +#define MAF_M_WB_PENDING (1< 3 SET_EN RW,1 Set enable +** <12> 1 BLK_SIZE RW,1 Scache/Bcache block size select +** <11:08> 4 FB_DP RW,0 Force bad data parity +** <07:02> 6 TAG_STAT RW Tag status and parity +** <1> 1 FLUSH RW,0 If set, clear all tag valid bits +** <0> 1 FHIT RW,0 Force hits +** +*/ + +#define SC_V_SET_EN 13 +#define SC_M_SET_EN (7< 1 DIS_VIC_BUF WO,0 Disable Scache victim buffer +** <26> 1 DIS_BAF_BYP WO,0 Disable speculative Bcache reads +** <25> 1 DBG_MUX_SEL WO,0 Debug MUX select +** <24:19> 6 PM_MUX_SEL WO,0 Performance counter MUX select +** <18:17> 2 BC_WAVE WO,0 Number of cycles of wave pipelining +** <16> 1 TL_PIPE_LATCH WO,0 Pipe system control pins +** <15> 1 EI_DIS_ERR WO,1 Disable ECC (parity) error +** <14:13> 2 BC_BAD_DAT WO,0 Force bad data +** <12:08> 5 BC_TAG_STAT WO Bcache tag status and parity +** <7> 1 BC_FHIT WO,0 Bcache force hit +** <6> 1 EI_ECC WO,1 ECC or byte parity mode +** <5> 1 VTM_FIRST WO,1 Drive out victim block address first +** <4> 1 CORR_FILL_DAT WO,1 Correct fill data +** <3> 1 EI_CMD_GRP3 WO,0 Drive MB command to external pins +** <2> 1 EI_CMD_GRP2 WO,0 Drive LOCK & SET_DIRTY to ext. pins +** <1> 1 ALLOC_CYC WO,0 Allocate cycle for non-cached LDs. +** <0> 1 BC_ENA W0,0 Bcache enable +** +*/ +#define BC_V_DIS_SC_VIC_BUF 27 +#define BC_M_DIS_SC_VIC_BUF (1<>1) +/* +** +** Bcache Configuration Register (BC_CONFIG) Bit Summary +** +** Extent Size Name Type Function +** ------ ---- ---- ---- --------------------------------- +** <35:29> 7 RSVD WO Reserved - Must Be Zero +** <28:20> 9 WE_CTL WO,0 Bcache write enable control +** <19:19> 1 RSVD WO,0 Reserved - Must Be Zero +** <18:16> 3 WE_OFF WO,1 Bcache fill write enable pulse offset +** <15:15> 1 RSVD WO,0 Reserved - Must Be Zero +** <14:12> 3 RD_WR_SPC WO,7 Bcache private read/write spacing +** <11:08> 4 WR_SPD WO,4 Bcache write speed in CPU cycles +** <07:04> 4 RD_SPD WO,4 Bcache read speed in CPU cycles +** <03:03> 1 RSVD WO,0 Reserved - Must Be Zero +** <02:00> 3 SIZE WO,1 Bcache size +*/ +#define BC_V_WE_CTL 20 +#define BC_M_WE_CTL (0x1FF< = 1. +*/ + +#define p0 r8 /* ITB/DTB Miss Scratch */ +#define p1 r9 /* ITB/DTB Miss Scratch */ +#define p2 r10 /* ITB/DTB Miss Scratch */ +#define p3 r11 +// #define ps r11 /* Processor Status */ +#define p4 r12 /* Local Scratch */ +#define p5 r13 /* Local Scratch */ +#define p6 r14 /* Local Scratch */ +#define p7 r25 /* Local Scratch */ + +/* +** SRM Defined State Definitions: +*/ + +/* +** This table is an accounting of the DECchip 21164 storage used to +** implement the SRM defined state for OSF/1. +** +** IPR Name Internal Storage +** -------- ---------------- +** Processor Status ps, dtbCm, ipl, r11 +** Program Counter Ibox +** Interrupt Entry ptEntInt +** Arith Trap Entry ptEntArith +** MM Fault Entry ptEntMM +** Unaligned Access Entry ptEntUna +** Instruction Fault Entry ptEntIF +** Call System Entry ptEntSys +** User Stack Pointer ptUsp +** Kernel Stack Pointer ptKsp +** Kernel Global Pointer ptKgp +** System Value ptSysVal +** Page Table Base Register ptPtbr +** Virtual Page Table Base iVptBr, mVptBr +** Process Control Block Base ptPcbb +** Address Space Number itbAsn, dtbAsn +** Cycle Counter cc, ccCtl +** Float Point Enable icsr +** Lock Flag Cbox/System +** Unique PCB +** Who-Am-I ptWhami +*/ + +#define ptEntUna pt2 /* Unaligned Access Dispatch Entry */ +#define ptImpure pt3 /* Pointer To PAL Scratch Area */ +#define ptEntIF pt7 /* Instruction Fault Dispatch Entry */ +#define ptIntMask pt8 /* Interrupt Enable Mask */ +#define ptEntSys pt9 /* Call System Dispatch Entry */ +#define ptTrap pt11 +#define ptEntInt pt11 /* Hardware Interrupt Dispatch Entry */ +#define ptEntArith pt12 /* Arithmetic Trap Dispatch Entry */ +#if defined(KDEBUG) +#define ptEntDbg pt13 /* Kernel Debugger Dispatch Entry */ +#endif /* KDEBUG */ +#define ptMisc pt16 /* Miscellaneous Flags */ +#define ptWhami pt16 /* Who-Am-I Register Pt16<15:8> */ +#define ptMces pt16 /* Machine Check Error Summary Pt16<4:0> */ +#define ptSysVal pt17 /* Per-Processor System Value */ +#define ptUsp pt18 /* User Stack Pointer */ +#define ptKsp pt19 /* Kernel Stack Pointer */ +#define ptPtbr pt20 /* Page Table Base Register */ +#define ptEntMM pt21 /* MM Fault Dispatch Entry */ +#define ptKgp pt22 /* Kernel Global Pointer */ +#define ptPcbb pt23 /* Process Control Block Base */ + +/* +** +** Miscellaneous PAL State Flags (ptMisc) Bit Summary +** +** Extent Size Name Function +** ------ ---- ---- --------------------------------- +** <55:48> 8 SWAP Swap PALcode flag -- character 'S' +** <47:32> 16 MCHK Machine Check Error code +** <31:16> 16 SCB System Control Block vector +** <15:08> 8 WHAMI Who-Am-I identifier +** <04:00> 5 MCES Machine Check Error Summary bits +** +*/ + +#define PT16_V_MCES 0 +#define PT16_V_WHAMI 8 +#define PT16_V_SCB 16 +#define PT16_V_MCHK 32 +#define PT16_V_SWAP 48 + +#endif /* DC21164FROMGASSOURCES_INCLUDED */ diff --git a/system/alpha/h/ev5_alpha_defs.h b/system/alpha/h/ev5_alpha_defs.h new file mode 100644 index 000000000..96769de04 --- /dev/null +++ b/system/alpha/h/ev5_alpha_defs.h @@ -0,0 +1,323 @@ +#ifndef EV5_ALPHA_DEFS_INCLUDED +#define EV5_ALPHA_DEFS_INCLUDED 1 + +// from ev5_alpha_defs.mar from Lance's fetch directory +// Lower-caseified and $ signs removed ... pb Nov/95 + +// .MACRO _ALPHADEFS +// ALPHADEF_VER == 6 ; Flag the version number of this file. +// .ENDM +// .MACRO _PSDEF,_GBL +// _DEFINI PS,_GBL +//;+ +//; PS Layout - PS +//; Loc Size name function +//; ------ ------ ______ ----------------------------------- +//; <31:29> 3 SA stack alignment +//; <31:13> 24 RES Reserved MBZ +//; <12:8> 5 IPL Priority level +//; <7> 1 VMM Virtual Mach Monitor +//; <6:5> 2 RES Reserved MBZ +//; <4:3> 2 CM Current Mode +//; <2> 1 IP Interrupt Pending +//; <1:0> 2 SW Software bits +//;- + +#define ps_v_sw 0 +#define ps_m_sw (3< 32 PFN Page Frame Number +//; <31:16> 16 SOFT Bits reserved for software use +//; <15> 1 UWE User write enable +//; <14> 1 SWE Super write enable +//; <13> 1 EWE Exec write enable +//; <12> 1 KWE Kernel write enable +//; <11> 1 URE User read enable +//; <10> 1 SRE Super read enable +//; <9> 1 ERE Exec read enable +//; <8> 1 KRE Kernel read enable +//; <7:6> 2 RES Reserved SBZ +//; <5> 1 HPF Huge Page Flag +//; <4> 1 ASM Wild card address space number match +//; <3> 1 FOE Fault On execute +//; <2> 1 FOW Fault On Write +//; <1> 1 FOR Fault On Read +//; <0> 1 V valid bit +//;- +// .MACRO _PTEDEF,_GBL +// _DEFINI PTE,_GBL + +#define pte_v_pfn 32 +#define pte_m_soft (0xFFFF0000) +#define pte_v_soft 16 +#define pte_m_uwe (0x8000) +#define pte_v_uwe 15 +#define pte_m_swe (0x4000) +#define pte_v_swe 14 +#define pte_m_ewe (0x2000) +#define pte_v_ewe 13 +#define pte_m_kwe (0x1000) +#define pte_v_kwe 12 +#define pte_m_ure (0x0800) +#define pte_v_ure 11 +#define pte_m_sre (0x0400) +#define pte_v_sre 10 +#define pte_m_ere (0x0200) +#define pte_v_ere 9 +#define pte_m_kre (0x0100) +#define pte_v_kre 8 +#define pte_m_hpf (0x0020) +#define pte_v_hpf 5 +#define pte_m_asm (0x0010) +#define pte_v_asm 4 +#define pte_m_foe (0x0008) +#define pte_v_foe 3 +#define pte_m_fow (0x0004) +#define pte_v_fow 2 +#define pte_m_for (0x0002) +#define pte_v_for 1 +#define pte_m_v (0x0001) +#define pte_v_v 0 + +// _DEFEND PTE,_GBL,DEF +// .ENDM +//;+ +//; VA layout - symbol prefix VA_ +//; +//; Loc Size name function +//; ------ ------ ------- ----------------------------------- +//; <42:33> 10 SEG1 First seg table offset for mapping +//; <32:23> 10 SEG2 Second seg table offset for mapping +//; <22:13> 10 SEG3 Third seg table offset for mapping +//; <12:0> 13 OFFSET Byte within page +//;- +// .MACRO _VADEF,_GBL +// _DEFINI VA,_GBL + +#define va_m_offset (0x000000001FFF) +#define va_v_offset 0 +#define va_m_seg3 (0x0000007FE000) +#define va_v_seg3 13 +#define va_m_seg2 (0x0001FF800000) +#define va_v_seg2 23 +#define va_m_seg1 (0x7FE00000000) +#define va_v_seg1 33 + +// _DEFEND VA,_GBL,DEF +// .ENDM +//;+ +//; PRIVILEGED CONTEXT BLOCK (PCB) +//;- +// .MACRO _PCBDEF,_GBL +// _DEFINI PCB,_GBL +#define pcb_q_ksp 0 +#define pcb_q_esp 8 +#define pcb_q_ssp 16 +#define pcb_q_usp 24 +#define pcb_q_ptbr 32 +#define pcb_q_asn 40 +#define pcb_q_ast 48 +#define pcb_q_fen 56 +#define pcb_q_cc 64 +#define pcb_q_unq 72 +#define pcb_q_sct 80 + +#define pcb_v_asten 0 +#define pcb_m_asten (0x0f< ; Software completion +// exs_v_inv <1> ; Ivalid operation +// exs_v_dze <2> ; Div by zero +// exs_v_fov <3> ; Floating point overflow +// exs_v_unf <4> ; Floating point underflow +// exs_v_ine <5> ; Floating point inexact +// exs_v_iov <6> ; Floating convert to integer overflow +#define exs_v_swc 0 +#define exs_v_inv 1 +#define exs_v_dze 2 +#define exs_v_fov 3 +#define exs_v_unf 4 +#define exs_v_ine 5 +#define exs_v_iov 6 + +#define exs_m_swc (1< ; machine check in progress +// mces_v_sce <1> ; system correctable error +// mces_v_pce <2> ; processor correctable error +// mces_v_dpc <3> ; disable reporting of processor correctable errors +// mces_v_dsc <4> ; disable reporting of system correctable errors +#define mces_v_mchk 0 +#define mces_v_sce 1 +#define mces_v_pce 2 +#define mces_v_dpc 3 +#define mces_v_dsc 4 + +#define mces_m_mchk (1<,..COL=<:> +// EV5$K_REVISION'..equ'34 +// In the definitions below, registers are annotated with one of the following +// symbols: +// +// RW - The register may be read and written +// RO - The register may only be read +// WO - The register may only be written +// +// For RO and WO registers, all bits and fields within the register are also +// read-only or write-only. For RW registers, each bit or field within +// the register is annotated with one of the following: +// +// RW - The bit/field may be read and written +// RO - The bit/field may be read; writes are ignored +// WO - The bit/field may be written; reads return an UNPREDICTABLE result. +// WZ - The bit/field may be written; reads return a 0 +// WC - The bit/field may be read; writes cause state to clear +// RC - The bit/field may be read, which also causes state to clear; writes are ignored +// Architecturally-defined (SRM) registers for EVMS +#define pt0 320 +#define pt1 321 +#define pt2 322 +#define pt3 323 +#define pt4 324 +#define pt5 325 +#define pt6 326 +#define pt7 327 +#define pt8 328 +#define pt9 329 +#define pt10 330 +#define pt11 331 +#define pt12 332 +#define pt13 333 +#define pt14 334 +#define pt15 335 +#define pt16 336 +#define pt17 337 +#define pt18 338 +#define pt19 339 +#define pt20 340 +#define pt21 341 +#define pt22 342 +#define pt23 343 +#define cbox_ipr_offset 16777200 +#define sc_ctl 168 +#define sc_stat 232 +#define sc_addr 392 +#define sc_addr_nm 392 +#define sc_addr_fhm 392 +#define bc_ctl 296 +#define bc_config 456 +#define ei_stat 360 +#define ei_addr 328 +#define fill_syn 104 +#define bc_tag_addr 264 +#define ld_lock 488 +#define aster 266 +#define astrr 265 +#define exc_addr 267 +#define exc_sum 268 +#define exc_mask 269 +#define hwint_clr 277 +#define ic_flush_ctl 281 +#define icperr_stat 282 +#define ic_perr_stat 282 +#define ic_row_map 283 +#define icsr 280 +#define ifault_va_form 274 +#define intid 273 +#define ipl 272 +#define isr 256 +#define itb_is 263 +#define itb_asn 259 +#define itb_ia 261 +#define itb_iap 262 +#define itb_pte 258 +#define itb_pte_temp 260 +#define itb_tag 257 +#define ivptbr 275 +#define pal_base 270 +#define pmctr 284 +// this is not the register ps .. pb #define ps 271 +#define sirr 264 +#define sl_txmit 278 +#define sl_rcv 279 +#define alt_mode 524 +#define cc 525 +#define cc_ctl 526 +#define dc_flush 528 +#define dcperr_stat 530 +#define dc_test_ctl 531 +#define dc_test_tag 532 +#define dc_test_tag_temp 533 +#define dtb_asn 512 +#define dtb_cm 513 +#define dtb_ia 522 +#define dtb_iap 521 +#define dtb_is 523 +#define dtb_pte 515 +#define dtb_pte_temp 516 +#define dtb_tag 514 +#define mcsr 527 +#define dc_mode 534 +#define maf_mode 535 +#define mm_stat 517 +#define mvptbr 520 +#define va 518 +#define va_form 519 +#define ev5_srm__ps 0 +#define ev5_srm__pc 0 +#define ev5_srm__asten 0 +#define ev5_srm__astsr 0 +#define ev5_srm__ipir 0 +#define ev5_srm__ipl 0 +#define ev5_srm__mces 0 +#define ev5_srm__pcbb 0 +#define ev5_srm__prbr 0 +#define ev5_srm__ptbr 0 +#define ev5_srm__scbb 0 +#define ev5_srm__sirr 0 +#define ev5_srm__sisr 0 +#define ev5_srm__tbchk 0 +#define ev5_srm__tb1a 0 +#define ev5_srm__tb1ap 0 +#define ev5_srm__tb1ad 0 +#define ev5_srm__tb1ai 0 +#define ev5_srm__tbis 0 +#define ev5_srm__ksp 0 +#define ev5_srm__esp 0 +#define ev5_srm__ssp 0 +#define ev5_srm__usp 0 +#define ev5_srm__vptb 0 +#define ev5_srm__whami 0 +#define ev5_srm__cc 0 +#define ev5_srm__unq 0 +// processor-specific iprs. +#define ev5__sc_ctl 168 +#define ev5__sc_stat 232 +#define ev5__sc_addr 392 +#define ev5__bc_ctl 296 +#define ev5__bc_config 456 +#define bc_config_k_size_1mb 1 +#define bc_config_k_size_2mb 2 +#define bc_config_k_size_4mb 3 +#define bc_config_k_size_8mb 4 +#define bc_config_k_size_16mb 5 +#define bc_config_k_size_32mb 6 +#define bc_config_k_size_64mb 7 +#define ev5__ei_stat 360 +#define ev5__ei_addr 328 +#define ev5__fill_syn 104 +#define ev5__bc_tag_addr 264 +#define ev5__aster 266 +#define ev5__astrr 265 +#define ev5__exc_addr 267 +#define exc_addr_v_pa 2 +#define exc_addr_s_pa 62 +#define ev5__exc_sum 268 +#define ev5__exc_mask 269 +#define ev5__hwint_clr 277 +#define ev5__ic_flush_ctl 281 +#define ev5__icperr_stat 282 +#define ev5__ic_perr_stat 282 +#define ev5__ic_row_map 283 +#define ev5__icsr 280 +#define ev5__ifault_va_form 274 +#define ev5__ifault_va_form_nt 274 +#define ifault_va_form_nt_v_vptb 30 +#define ifault_va_form_nt_s_vptb 34 +#define ev5__intid 273 +#define ev5__ipl 272 +#define ev5__itb_is 263 +#define ev5__itb_asn 259 +#define ev5__itb_ia 261 +#define ev5__itb_iap 262 +#define ev5__itb_pte 258 +#define ev5__itb_pte_temp 260 +#define ev5__itb_tag 257 +#define ev5__ivptbr 275 +#define ivptbr_v_vptb 30 +#define ivptbr_s_vptb 34 +#define ev5__pal_base 270 +#define ev5__pmctr 284 +#define ev5__ps 271 +#define ev5__isr 256 +#define ev5__sirr 264 +#define ev5__sl_txmit 278 +#define ev5__sl_rcv 279 +#define ev5__alt_mode 524 +#define ev5__cc 525 +#define ev5__cc_ctl 526 +#define ev5__dc_flush 528 +#define ev5__dcperr_stat 530 +#define ev5__dc_test_ctl 531 +#define ev5__dc_test_tag 532 +#define ev5__dc_test_tag_temp 533 +#define ev5__dtb_asn 512 +#define ev5__dtb_cm 513 +#define ev5__dtb_ia 522 +#define ev5__dtb_iap 521 +#define ev5__dtb_is 523 +#define ev5__dtb_pte 515 +#define ev5__dtb_pte_temp 516 +#define ev5__dtb_tag 514 +#define ev5__mcsr 527 +#define ev5__dc_mode 534 +#define ev5__maf_mode 535 +#define ev5__mm_stat 517 +#define ev5__mvptbr 520 +#define ev5__va 518 +#define ev5__va_form 519 +#define ev5__va_form_nt 519 +#define va_form_nt_s_va 19 +#define va_form_nt_v_vptb 30 +#define va_form_nt_s_vptb 34 +#define ev5s_ev5_def 10 +#define ev5_def 0 +// cbox registers. +#define sc_ctl_v_sc_fhit 0 +#define sc_ctl_v_sc_flush 1 +#define sc_ctl_s_sc_tag_stat 6 +#define sc_ctl_v_sc_tag_stat 2 +#define sc_ctl_s_sc_fb_dp 4 +#define sc_ctl_v_sc_fb_dp 8 +#define sc_ctl_v_sc_blk_size 12 +#define sc_ctl_s_sc_set_en 3 +#define sc_ctl_v_sc_set_en 13 +#define sc_ctl_s_sc_soft_repair 3 +#define sc_ctl_v_sc_soft_repair 16 +#define sc_stat_s_sc_tperr 3 +#define sc_stat_v_sc_tperr 0 +#define sc_stat_s_sc_dperr 8 +#define sc_stat_v_sc_dperr 3 +#define sc_stat_s_cbox_cmd 5 +#define sc_stat_v_cbox_cmd 11 +#define sc_stat_v_sc_scnd_err 16 +#define sc_addr_fhm_v_sc_tag_parity 4 +#define sc_addr_fhm_s_tag_stat_sb0 3 +#define sc_addr_fhm_v_tag_stat_sb0 5 +#define sc_addr_fhm_s_tag_stat_sb1 3 +#define sc_addr_fhm_v_tag_stat_sb1 8 +#define sc_addr_fhm_s_ow_mod0 2 +#define sc_addr_fhm_v_ow_mod0 11 +#define sc_addr_fhm_s_ow_mod1 2 +#define sc_addr_fhm_v_ow_mod1 13 +#define sc_addr_fhm_s_tag_lo 17 +#define sc_addr_fhm_v_tag_lo 15 +#define sc_addr_fhm_s_tag_hi 7 +#define sc_addr_fhm_v_tag_hi 32 +#define bc_ctl_v_bc_enabled 0 +#define bc_ctl_v_alloc_cyc 1 +#define bc_ctl_v_ei_opt_cmd 2 +#define bc_ctl_v_ei_opt_cmd_mb 3 +#define bc_ctl_v_corr_fill_dat 4 +#define bc_ctl_v_vtm_first 5 +#define bc_ctl_v_ei_ecc_or_parity 6 +#define bc_ctl_v_bc_fhit 7 +#define bc_ctl_s_bc_tag_stat 5 +#define bc_ctl_v_bc_tag_stat 8 +#define bc_ctl_s_bc_bad_dat 2 +#define bc_ctl_v_bc_bad_dat 13 +#define bc_ctl_v_ei_dis_err 15 +#define bc_ctl_v_tl_pipe_latch 16 +#define bc_ctl_s_bc_wave_pipe 2 +#define bc_ctl_v_bc_wave_pipe 17 +#define bc_ctl_s_pm_mux_sel 6 +#define bc_ctl_v_pm_mux_sel 19 +#define bc_ctl_v_dbg_mux_sel 25 +#define bc_ctl_v_dis_baf_byp 26 +#define bc_ctl_v_dis_sc_vic_buf 27 +#define bc_ctl_v_dis_sys_addr_par 28 +#define bc_ctl_v_read_dirty_cln_shr 29 +#define bc_ctl_v_write_read_bubble 30 +#define bc_ctl_v_bc_wave_pipe_2 31 +#define bc_ctl_v_auto_dack 32 +#define bc_ctl_v_dis_byte_word 33 +#define bc_ctl_v_stclk_delay 34 +#define bc_ctl_v_write_under_miss 35 +#define bc_config_s_bc_size 3 +#define bc_config_v_bc_size 0 +#define bc_config_s_bc_rd_spd 4 +#define bc_config_v_bc_rd_spd 4 +#define bc_config_s_bc_wr_spd 4 +#define bc_config_v_bc_wr_spd 8 +#define bc_config_s_bc_rd_wr_spc 3 +#define bc_config_v_bc_rd_wr_spc 12 +#define bc_config_s_fill_we_offset 3 +#define bc_config_v_fill_we_offset 16 +#define bc_config_s_bc_we_ctl 9 +#define bc_config_v_bc_we_ctl 20 +// cbox registers, continued +#define ei_stat_s_sys_id 4 +#define ei_stat_v_sys_id 24 +#define ei_stat_v_bc_tperr 28 +#define ei_stat_v_bc_tc_perr 29 +#define ei_stat_v_ei_es 30 +#define ei_stat_v_cor_ecc_err 31 +#define ei_stat_v_unc_ecc_err 32 +#define ei_stat_v_ei_par_err 33 +#define ei_stat_v_fil_ird 34 +#define ei_stat_v_seo_hrd_err 35 +// +#define bc_tag_addr_v_hit 12 +#define bc_tag_addr_v_tagctl_p 13 +#define bc_tag_addr_v_tagctl_d 14 +#define bc_tag_addr_v_tagctl_s 15 +#define bc_tag_addr_v_tagctl_v 16 +#define bc_tag_addr_v_tag_p 17 +#define bc_tag_addr_s_bc_tag 19 +#define bc_tag_addr_v_bc_tag 20 +// ibox and icache registers. +#define aster_v_kar 0 +#define aster_v_ear 1 +#define aster_v_sar 2 +#define aster_v_uar 3 +#define astrr_v_kar 0 +#define astrr_v_ear 1 +#define astrr_v_sar 2 +#define astrr_v_uar 3 +#define exc_addr_v_pal 0 +#define exc_sum_v_swc 10 +#define exc_sum_v_inv 11 +#define exc_sum_v_dze 12 +#define exc_sum_v_fov 13 +#define exc_sum_v_unf 14 +#define exc_sum_v_ine 15 +#define exc_sum_v_iov 16 +#define hwint_clr_v_pc0c 27 +#define hwint_clr_v_pc1c 28 +#define hwint_clr_v_pc2c 29 +#define hwint_clr_v_crdc 32 +#define hwint_clr_v_slc 33 +// ibox and icache registers, continued +#define icperr_stat_v_dpe 11 +#define icperr_stat_v_tpe 12 +#define icperr_stat_v_tmr 13 +#define ic_perr_stat_v_dpe 11 +#define ic_perr_stat_v_tpe 12 +#define ic_perr_stat_v_tmr 13 +#define icsr_v_pma 8 +#define icsr_v_pmp 9 +#define icsr_v_byt 17 +#define icsr_v_fmp 18 +#define icsr_v_im0 20 +#define icsr_v_im1 21 +#define icsr_v_im2 22 +#define icsr_v_im3 23 +#define icsr_v_tmm 24 +#define icsr_v_tmd 25 +#define icsr_v_fpe 26 +#define icsr_v_hwe 27 +#define icsr_s_spe 2 +#define icsr_v_spe 28 +#define icsr_v_sde 30 +#define icsr_v_crde 32 +#define icsr_v_sle 33 +#define icsr_v_fms 34 +#define icsr_v_fbt 35 +#define icsr_v_fbd 36 +#define icsr_v_dbs 37 +#define icsr_v_ista 38 +#define icsr_v_tst 39 +#define ifault_va_form_s_va 30 +#define ifault_va_form_v_va 3 +#define ifault_va_form_s_vptb 31 +#define ifault_va_form_v_vptb 33 +#define ifault_va_form_nt_s_va 19 +#define ifault_va_form_nt_v_va 3 +#define intid_s_intid 5 +#define intid_v_intid 0 +// ibox and icache registers, continued +#define ipl_s_ipl 5 +#define ipl_v_ipl 0 +#define itb_is_s_va 30 +#define itb_is_v_va 13 +#define itb_asn_s_asn 7 +#define itb_asn_v_asn 4 +#define itb_pte_v_asm 4 +#define itb_pte_s_gh 2 +#define itb_pte_v_gh 5 +#define itb_pte_v_kre 8 +#define itb_pte_v_ere 9 +#define itb_pte_v_sre 10 +#define itb_pte_v_ure 11 +#define itb_pte_s_pfn 27 +#define itb_pte_v_pfn 32 +#define itb_pte_temp_v_asm 13 +#define itb_pte_temp_v_kre 18 +#define itb_pte_temp_v_ere 19 +#define itb_pte_temp_v_sre 20 +#define itb_pte_temp_v_ure 21 +#define itb_pte_temp_s_gh 3 +#define itb_pte_temp_v_gh 29 +#define itb_pte_temp_s_pfn 27 +#define itb_pte_temp_v_pfn 32 +// ibox and icache registers, continued +#define itb_tag_s_va 30 +#define itb_tag_v_va 13 +#define pal_base_s_pal_base 26 +#define pal_base_v_pal_base 14 +#define pmctr_s_sel2 4 +#define pmctr_v_sel2 0 +#define pmctr_s_sel1 4 +#define pmctr_v_sel1 4 +#define pmctr_v_killk 8 +#define pmctr_v_killp 9 +#define pmctr_s_ctl2 2 +#define pmctr_v_ctl2 10 +#define pmctr_s_ctl1 2 +#define pmctr_v_ctl1 12 +#define pmctr_s_ctl0 2 +#define pmctr_v_ctl0 14 +#define pmctr_s_ctr2 14 +#define pmctr_v_ctr2 16 +#define pmctr_v_killu 30 +#define pmctr_v_sel0 31 +#define pmctr_s_ctr1 16 +#define pmctr_v_ctr1 32 +#define pmctr_s_ctr0 16 +#define pmctr_v_ctr0 48 +#define ps_v_cm0 3 +#define ps_v_cm1 4 +#define isr_s_astrr 4 +#define isr_v_astrr 0 +#define isr_s_sisr 15 +#define isr_v_sisr 4 +#define isr_v_atr 19 +#define isr_v_i20 20 +#define isr_v_i21 21 +#define isr_v_i22 22 +#define isr_v_i23 23 +#define isr_v_pc0 27 +#define isr_v_pc1 28 +#define isr_v_pc2 29 +#define isr_v_pfl 30 +#define isr_v_mck 31 +#define isr_v_crd 32 +#define isr_v_sli 33 +#define isr_v_hlt 34 +#define sirr_s_sirr 15 +#define sirr_v_sirr 4 +// ibox and icache registers, continued +#define sl_txmit_v_tmt 7 +#define sl_rcv_v_rcv 6 +// mbox and dcache registers. +#define alt_mode_v_am0 3 +#define alt_mode_v_am1 4 +#define cc_ctl_v_cc_ena 32 +#define dcperr_stat_v_seo 0 +#define dcperr_stat_v_lock 1 +#define dcperr_stat_v_dp0 2 +#define dcperr_stat_v_dp1 3 +#define dcperr_stat_v_tp0 4 +#define dcperr_stat_v_tp1 5 +// the following two registers are used exclusively for test and diagnostics. +// they should not be referenced in normal operation. +#define dc_test_ctl_v_bank0 0 +#define dc_test_ctl_v_bank1 1 +#define dc_test_ctl_v_fill_0 2 +#define dc_test_ctl_s_index 10 +#define dc_test_ctl_v_index 3 +#define dc_test_ctl_s_fill_1 19 +#define dc_test_ctl_v_fill_1 13 +#define dc_test_ctl_s_fill_2 32 +#define dc_test_ctl_v_fill_2 32 +// mbox and dcache registers, continued. +#define dc_test_tag_v_tag_par 2 +#define dc_test_tag_v_ow0 11 +#define dc_test_tag_v_ow1 12 +#define dc_test_tag_s_tag 26 +#define dc_test_tag_v_tag 13 +#define dc_test_tag_temp_v_tag_par 2 +#define dc_test_tag_temp_v_d0p0 3 +#define dc_test_tag_temp_v_d0p1 4 +#define dc_test_tag_temp_v_d1p0 5 +#define dc_test_tag_temp_v_d1p1 6 +#define dc_test_tag_temp_v_ow0 11 +#define dc_test_tag_temp_v_ow1 12 +#define dc_test_tag_temp_s_tag 26 +#define dc_test_tag_temp_v_tag 13 +#define dtb_asn_s_asn 7 +#define dtb_asn_v_asn 57 +#define dtb_cm_v_cm0 3 +#define dtb_cm_v_cm1 4 +#define dtbis_s_va0 30 +#define dtbis_v_va0 13 +#define dtb_pte_v_for 1 +#define dtb_pte_v_fow 2 +#define dtb_pte_v_asm 4 +#define dtb_pte_s_gh 2 +#define dtb_pte_v_gh 5 +#define dtb_pte_v_kre 8 +#define dtb_pte_v_ere 9 +#define dtb_pte_v_sre 10 +#define dtb_pte_v_ure 11 +#define dtb_pte_v_kwe 12 +#define dtb_pte_v_ewe 13 +#define dtb_pte_v_swe 14 +#define dtb_pte_v_uwe 15 +#define dtb_pte_s_pfn 27 +#define dtb_pte_v_pfn 32 +// mbox and dcache registers, continued. +#define dtb_pte_temp_v_for 0 +#define dtb_pte_temp_v_fow 1 +#define dtb_pte_temp_v_kre 2 +#define dtb_pte_temp_v_ere 3 +#define dtb_pte_temp_v_sre 4 +#define dtb_pte_temp_v_ure 5 +#define dtb_pte_temp_v_kwe 6 +#define dtb_pte_temp_v_ewe 7 +#define dtb_pte_temp_v_swe 8 +#define dtb_pte_temp_v_uwe 9 +#define dtb_pte_temp_v_asm 10 +#define dtb_pte_temp_s_fill_0 2 +#define dtb_pte_temp_v_fill_0 11 +#define dtb_pte_temp_s_pfn 27 +#define dtb_pte_temp_v_pfn 13 +#define dtb_tag_s_va 30 +#define dtb_tag_v_va 13 +// most mcsr bits are used for testability and diagnostics only. +// for normal operation, they will be supported in the following configuration: +// split_dcache = 1, maf_nomerge = 0, wb_flush_always = 0, wb_nomerge = 0, +// dc_ena<1:0> = 1, dc_fhit = 0, dc_bad_parity = 0 +#define mcsr_v_big_endian 0 +#define mcsr_v_sp0 1 +#define mcsr_v_sp1 2 +#define mcsr_v_mbox_sel 3 +#define mcsr_v_e_big_endian 4 +#define mcsr_v_dbg_packet_sel 5 +#define dc_mode_v_dc_ena 0 +#define dc_mode_v_dc_fhit 1 +#define dc_mode_v_dc_bad_parity 2 +#define dc_mode_v_dc_perr_dis 3 +#define dc_mode_v_dc_doa 4 +#define maf_mode_v_maf_nomerge 0 +#define maf_mode_v_wb_flush_always 1 +#define maf_mode_v_wb_nomerge 2 +#define maf_mode_v_io_nomerge 3 +#define maf_mode_v_wb_cnt_disable 4 +#define maf_mode_v_maf_arb_disable 5 +#define maf_mode_v_dread_pending 6 +#define maf_mode_v_wb_pending 7 +// mbox and dcache registers, continued. +#define mm_stat_v_wr 0 +#define mm_stat_v_acv 1 +#define mm_stat_v_for 2 +#define mm_stat_v_fow 3 +#define mm_stat_v_dtb_miss 4 +#define mm_stat_v_bad_va 5 +#define mm_stat_s_ra 5 +#define mm_stat_v_ra 6 +#define mm_stat_s_opcode 6 +#define mm_stat_v_opcode 11 +#define mvptbr_s_vptb 31 +#define mvptbr_v_vptb 33 +#define va_form_s_va 30 +#define va_form_v_va 3 +#define va_form_s_vptb 31 +#define va_form_v_vptb 33 +#define va_form_nt_s_va 19 +#define va_form_nt_v_va 3 +//.endm + +#endif diff --git a/system/alpha/h/ev5_impure.h b/system/alpha/h/ev5_impure.h new file mode 100644 index 000000000..ffa910ce2 --- /dev/null +++ b/system/alpha/h/ev5_impure.h @@ -0,0 +1,423 @@ +#ifndef EV5_IMPURE_INCLUDED +#define EV5_IMPURE_INCLUDED + +/* +// This uses the Hudson file format from "impure.h" but with the fields from +// the distrubuted palcode "ev5_impure.sdl" .. pboyle Nov/95 + +//orig file: impure.sdl +//orig +//orig Abstract: PAL impure scratch area and logout area data structure definitions for +//orig Alpha firmware. +//orig +//orig +//orig module $pal_impure; +//orig +//orig Edit Date Who Description +//orig ---- --------- --- --------------------- +//orig 1 7-Jul-93 JEM Initial Entry +//orig 2 18-nov-93 JEM Add shadow bc_ctl and pmctr_ctl to impure area +//orig Delete mvptbr +//orig Calculate pal$logout from end of impure area +//orig 3 6-dec-93 JEM Add pmctr_ctl bitfield definitions +//orig 4 3-feb-94 JEM Remove f31,r31 from impure area; Remove bc_ctl, pmctr_ctl; +//orig add ic_perr_stat, pmctr, dc_perr_stat, sc_stat, sc_addr, sc_ctl, +//orig bc_tag_addr, ei_stat, ei_addr, fill_syn, ld_lock +//orig 5 19-feb-94 JEM add gpr constants, and add f31,r31 back in to be consistent with ev4 +//orig add cns$ipr_offset +//orig 6 18-apr-94 JEM Add shadow bc_ctl and pmctr_ctl to impure area again. +//orig 7 18-jul-94 JEM Add bc_config shadow. Add mchk$sys_base constant to mchk logout frame +//orig +//orig +//orig constant REVISION equals 7 prefix IMPURE$; // Revision number of this file +//orig + +** Macros for saving/restoring data to/from the PAL impure scratch +** area. +** +** The console save state area is larger than the addressibility +** of the HW_LD/ST instructions (10-bit signed byte displacement), +** so some adjustments to the base offsets, as well as the offsets +** within each base region, are necessary. +** +** The console save state area is divided into two segments; the +** CPU-specific segment and the platform-specific segment. The +** state that is saved in the CPU-specific segment includes GPRs, +** FPRs, IPRs, halt code, MCHK flag, etc. All other state is saved +** in the platform-specific segment. +** +** The impure pointer will need to be adjusted by a different offset +** value for each region within a given segment. The SAVE and RESTORE +** macros will auto-magically adjust the offsets accordingly. +** +*/ +#if 0 +#define SAVE_GPR(reg,offset,base) \ + stq_p reg, ((offset-0x200)&0x3FF)(base) + +#define RESTORE_GPR(reg,offset,base) \ + ldq_p reg, ((offset-0x200)&0x3FF)(base) + + +#define SAVE_FPR(reg,offset,base) \ + stt reg, ((offset-0x200)&0x3FF)(base) + +#define RESTORE_FPR(reg,offset,base) \ + ldt reg, ((offset-0x200)&0x3FF)(base) + +#define SAVE_IPR(reg,offset,base) \ + mfpr v0, reg; \ + stq_p v0, ((offset-CNS_Q_IPR)&0x3FF)(base) + +#define RESTORE_IPR(reg,offset,base) \ + ldq_p v0, ((offset-CNS_Q_IPR)&0x3FF)(base); \ + mtpr v0, reg + +#define SAVE_SHADOW(reg,offset,base) \ + stq_p reg, ((offset-CNS_Q_IPR)&0x3FF)(base) + +#define RESTORE_SHADOW(reg,offset,base)\ + ldq_p reg, ((offset-CNS_Q_IPR)&0x3FF)(base) +#else +//#define SEXT10(X) (((X) & 0x200) ? ((X) | 0xfffffffffffffc00) : (X)) +#define SEXT10(X) ((X) & 0x3ff) +//#define SEXT10(X) (((X) << 55) >> 55) + +#define SAVE_GPR(reg,offset,base) \ + stq_p reg, (SEXT10(offset-0x200))(base) + +#define RESTORE_GPR(reg,offset,base) \ + ldq_p reg, (SEXT10(offset-0x200))(base) + + +#define SAVE_FPR(reg,offset,base) \ + stt reg, (SEXT10(offset-0x200))(base) + +#define RESTORE_FPR(reg,offset,base) \ + ldt reg, (SEXT10(offset-0x200))(base) + +#define SAVE_IPR(reg,offset,base) \ + mfpr v0, reg; \ + stq_p v0, (SEXT10(offset-CNS_Q_IPR))(base) + +#define RESTORE_IPR(reg,offset,base) \ + ldq_p v0, (SEXT10(offset-CNS_Q_IPR))(base); \ + mtpr v0, reg + +#define SAVE_SHADOW(reg,offset,base) \ + stq_p reg, (SEXT10(offset-CNS_Q_IPR))(base) + +#define RESTORE_SHADOW(reg,offset,base)\ + ldq_p reg, (SEXT10(offset-CNS_Q_IPR))(base) +#endif +/* orig Structure of the processor-specific impure area */ + +/* orig aggregate impure struct prefix "" tag ""; + * orig cns$flag quadword; + * orig cns$hlt quadword; +*/ + +/* Define base for debug monitor compatibility */ +#define CNS_Q_BASE 0x000 +#define CNS_Q_FLAG 0x100 +#define CNS_Q_HALT 0x108 + + +/* orig constant ( + * orig cns$r0,cns$r1,cns$r2,cns$r3,cns$r4,cns$r5,cns$r6,cns$r7, + * orig cns$r8,cns$r9,cns$r10,cns$r11,cns$r12,cns$r13,cns$r14,cns$r15, + * orig cns$r16,cns$r17,cns$r18,cns$r19,cns$r20,cns$r21,cns$r22,cns$r23, + * orig cns$r24,cns$r25,cns$r26,cns$r27,cns$r28,cns$r29,cns$r30,cns$r31 + * orig ) equals . increment 8 prefix "" tag ""; + * orig cns$gpr quadword dimension 32; +*/ +/* Offset to base of saved GPR area - 32 quadword */ +#define CNS_Q_GPR 0x110 +#define cns_gpr CNS_Q_GPR + +/* orig constant ( + * orig cns$f0,cns$f1,cns$f2,cns$f3,cns$f4,cns$f5,cns$f6,cns$f7, + * orig cns$f8,cns$f9,cns$f10,cns$f11,cns$f12,cns$f13,cns$f14,cns$f15, + * orig cns$f16,cns$f17,cns$f18,cns$f19,cns$f20,cns$f21,cns$f22,cns$f23, + * orig cns$f24,cns$f25,cns$f26,cns$f27,cns$f28,cns$f29,cns$f30,cns$f31 + * orig ) equals . increment 8 prefix "" tag ""; + * orig cns$fpr quadword dimension 32; +*/ +/* Offset to base of saved FPR area - 32 quadwords */ +#define CNS_Q_FPR 0x210 + +/* orig #t=.; + * orig cns$mchkflag quadword; +*/ +#define CNS_Q_MCHK 0x310 + +/* orig constant cns$pt_offset equals .; + * orig constant ( + * orig cns$pt0,cns$pt1,cns$pt2,cns$pt3,cns$pt4,cns$pt5,cns$pt6, + * orig cns$pt7,cns$pt8,cns$pt9,cns$pt10,cns$pt11,cns$pt12,cns$pt13, + * orig cns$pt14,cns$pt15,cns$pt16,cns$pt17,cns$pt18,cns$pt19,cns$pt20, + * orig cns$pt21,cns$pt22,cns$pt23 + * orig ) equals . increment 8 prefix "" tag ""; + * orig cns$pt quadword dimension 24; +*/ +/* Offset to base of saved PALtemp area - 25 quadwords */ +#define CNS_Q_PT 0x318 + +/* orig cns$shadow8 quadword; + * orig cns$shadow9 quadword; + * orig cns$shadow10 quadword; + * orig cns$shadow11 quadword; + * orig cns$shadow12 quadword; + * orig cns$shadow13 quadword; + * orig cns$shadow14 quadword; + * orig cns$shadow25 quadword; +*/ +/* Offset to base of saved PALshadow area - 8 quadwords */ +#define CNS_Q_SHADOW 0x3D8 + +/* Offset to base of saved IPR area */ +#define CNS_Q_IPR 0x418 + +/* orig constant cns$ipr_offset equals .; */ +/* orig cns$exc_addr quadword; */ +#define CNS_Q_EXC_ADDR 0x418 +/* orig cns$pal_base quadword; */ +#define CNS_Q_PAL_BASE 0x420 +/* orig cns$mm_stat quadword; */ +#define CNS_Q_MM_STAT 0x428 +/* orig cns$va quadword; */ +#define CNS_Q_VA 0x430 +/* orig cns$icsr quadword; */ +#define CNS_Q_ICSR 0x438 +/* orig cns$ipl quadword; */ +#define CNS_Q_IPL 0x440 +/* orig cns$ps quadword; // Ibox current mode */ +#define CNS_Q_IPS 0x448 +/* orig cns$itb_asn quadword; */ +#define CNS_Q_ITB_ASN 0x450 +/* orig cns$aster quadword; */ +#define CNS_Q_ASTER 0x458 +/* orig cns$astrr quadword; */ +#define CNS_Q_ASTRR 0x460 +/* orig cns$isr quadword; */ +#define CNS_Q_ISR 0x468 +/* orig cns$ivptbr quadword; */ +#define CNS_Q_IVPTBR 0x470 +/* orig cns$mcsr quadword; */ +#define CNS_Q_MCSR 0x478 +/* orig cns$dc_mode quadword; */ +#define CNS_Q_DC_MODE 0x480 +/* orig cns$maf_mode quadword; */ +#define CNS_Q_MAF_MODE 0x488 +/* orig cns$sirr quadword; */ +#define CNS_Q_SIRR 0x490 +/* orig cns$fpcsr quadword; */ +#define CNS_Q_FPCSR 0x498 +/* orig cns$icperr_stat quadword; */ +#define CNS_Q_ICPERR_STAT 0x4A0 +/* orig cns$pmctr quadword; */ +#define CNS_Q_PM_CTR 0x4A8 +/* orig cns$exc_sum quadword; */ +#define CNS_Q_EXC_SUM 0x4B0 +/* orig cns$exc_mask quadword; */ +#define CNS_Q_EXC_MASK 0x4B8 +/* orig cns$intid quadword; */ +#define CNS_Q_INT_ID 0x4C0 +/* orig cns$dcperr_stat quadword; */ +#define CNS_Q_DCPERR_STAT 0x4C8 +/* orig cns$sc_stat quadword; */ +#define CNS_Q_SC_STAT 0x4D0 +/* orig cns$sc_addr quadword; */ +#define CNS_Q_SC_ADDR 0x4D8 +/* orig cns$sc_ctl quadword; */ +#define CNS_Q_SC_CTL 0x4E0 +/* orig cns$bc_tag_addr quadword; */ +#define CNS_Q_BC_TAG_ADDR 0x4E8 +/* orig cns$ei_stat quadword; */ +#define CNS_Q_EI_STAT 0x4F0 +/* orig cns$ei_addr quadword; */ +#define CNS_Q_EI_ADDR 0x4F8 +/* orig cns$fill_syn quadword; */ +#define CNS_Q_FILL_SYN 0x500 +/* orig cns$ld_lock quadword; */ +#define CNS_Q_LD_LOCK 0x508 +/* orig cns$bc_ctl quadword; // shadow of on chip bc_ctl */ +#define CNS_Q_BC_CTL 0x510 +/* orig cns$pmctr_ctl quadword; // saved frequency select info for performance monitor counter */ +#define CNS_Q_PM_CTL 0x518 +/* orig cns$bc_config quadword; // shadow of on chip bc_config */ +#define CNS_Q_BC_CFG 0x520 + +/* orig constant cns$size equals .; + * orig + * orig constant pal$impure_common_size equals (%x0200 +7) & %xfff8; + * orig constant pal$impure_specific_size equals (.+7) & %xfff8; + * orig constant cns$mchksize equals (.+7-#t) & %xfff8; + * orig constant pal$logout_area equals pal$impure_specific_size ; + * orig end impure; +*/ + +/* This next set of stuff came from the old code ..pb */ +#define CNS_Q_SROM_REV 0x528 +#define CNS_Q_PROC_ID 0x530 +#define CNS_Q_MEM_SIZE 0x538 +#define CNS_Q_CYCLE_CNT 0x540 +#define CNS_Q_SIGNATURE 0x548 +#define CNS_Q_PROC_MASK 0x550 +#define CNS_Q_SYSCTX 0x558 + + + +#define MACHINE_CHECK_CRD_BASE 0 +#define MACHINE_CHECK_SIZE ((CNS_Q_SYSCTX + 7 - CNS_Q_MCHK) & 0xfff8) + + + +/* orig + * orig aggregate EV5PMCTRCTL_BITS structure fill prefix PMCTR_CTL$; + * orig SPROCESS bitfield length 1 ; + * orig FILL_0 bitfield length 3 fill tag $$; + * orig FRQ2 bitfield length 2 ; + * orig FRQ1 bitfield length 2 ; + * orig FRQ0 bitfield length 2 ; + * orig CTL2 bitfield length 2 ; + * orig CTL1 bitfield length 2 ; + * orig CTL0 bitfield length 2 ; + * orig FILL_1 bitfield length 16 fill tag $$; + * orig FILL_2 bitfield length 32 fill tag $$; + * orig end EV5PMCTRCTL_BITS; + * orig + * orig end_module $pal_impure; + * orig + * orig module $pal_logout; + * orig + * orig // + * orig // Start definition of Corrected Error Frame + * orig // + */ + +/* + * orig aggregate crd_logout struct prefix "" tag ""; + */ + +#ifdef SIMOS +#define pal_logout_area 0x600 +#define mchk_crd_base 0 +#endif + +/* orig mchk$crd_flag quadword; */ +#define mchk_crd_flag 0 +/* orig mchk$crd_offsets quadword; */ +#define mchk_crd_offsets 8 +/* orig + * orig // Pal-specific information */ +#define mchk_crd_mchk_code 0x10 +/* orig mchk$crd_mchk_code quadword; + * orig + * orig // CPU-specific information + * orig constant mchk$crd_cpu_base equals . ; + * orig mchk$crd_ei_addr quadword; */ +#define mchk_crd_ei_addr 0x18 +/* orig mchk$crd_fill_syn quadword; */ +#define mchk_crd_fill_syn 0x20 +/* orig mchk$crd_ei_stat quadword; */ +#define mchk_crd_ei_stat 0x28 +/* orig mchk$crd_isr quadword; */ +#define mchk_crd_isr 0x30 + +/* + * Hacked up constants for the turbolaser build. Hope + * this is moreless correct + */ + +#define mchk_crd_whami 0x38 +#define mchk_crd_tldev 0x40 +#define mchk_crd_tlber 0x48 +#define mchk_crd_tlesr0 0x50 +#define mchk_crd_tlesr1 0x58 +#define mchk_crd_tlesr2 0x60 +#define mchk_crd_tlesr3 0x68 +#define mchk_crd_rsvd 0x70 + + +#ifdef SIMOS +/* + * mchk area seems different for tlaser + */ + +#define mchk_crd_size 0x80 +#define mchk_mchk_base (mchk_crd_size) + +#define mchk_tlber 0x0 +#define mchk_tlepaerr 0x8 +#define mchk_tlepderr 0x10 +#define mchk_tlepmerr 0x18 + + +#endif + + +/* orig + * orig // System-specific information + * orig constant mchk$crd_sys_base equals . ; + * orig constant mchk$crd_size equals (.+7) & %xfff8; + * orig + * orig end crd_logout; + * orig // + * orig // Start definition of Machine check logout Frame + * orig // + * orig aggregate logout struct prefix "" tag ""; + * orig mchk$flag quadword; */ +/* orig mchk$offsets quadword; */ +/* orig + * orig // Pal-specific information + * orig mchk$mchk_code quadword; */ +/* + + * orig mchk$pt quadword dimension 24; + * orig + * orig // CPU-specific information + * orig constant mchk$cpu_base equals . ; + * orig mchk$exc_addr quadword; + * orig mchk$exc_sum quadword; + * orig mchk$exc_mask quadword; + * orig mchk$pal_base quadword; + * orig mchk$isr quadword; + * orig mchk$icsr quadword; + * orig mchk$ic_perr_stat quadword; + * orig mchk$dc_perr_stat quadword; + * orig mchk$va quadword; + * orig mchk$mm_stat quadword; + * orig mchk$sc_addr quadword; + * orig mchk$sc_stat quadword; + * orig mchk$bc_tag_addr quadword; + * orig mchk$ei_addr quadword; + * orig mchk$fill_syn quadword; + * orig mchk$ei_stat quadword; + * orig mchk$ld_lock quadword; + * orig + * orig // System-specific information + * orig + * orig constant mchk$sys_base equals . ; + * orig mchk$sys_ipr1 quadword ; // Holder for system-specific stuff + * orig + * orig constant mchk$size equals (.+7) & %xfff8; + * orig + * orig + * orig constant mchk$crd_base equals 0 ; + * orig constant mchk$mchk_base equals mchk$crd_size ; + * orig + * orig + * orig end logout; + * orig + * orig end_module $pal_logout; +*/ + + + + +/* this is lingering in the old ladbx code but looks like it was from ev4 days. + * This was 0x160 in the old days..pb +*/ +#define LAF_K_SIZE MACHINE_CHECK_SIZE +#endif diff --git a/system/alpha/h/ev5_osfalpha_defs.h b/system/alpha/h/ev5_osfalpha_defs.h new file mode 100644 index 000000000..08a110075 --- /dev/null +++ b/system/alpha/h/ev5_osfalpha_defs.h @@ -0,0 +1,160 @@ +#ifndef EV5_OSFALPHA_DEFS_INCLUDED +#define EV5_OSFALPHA_DEFS_INCLUDED 1 + + +// from ev5_osfalpha_defs.mar from Lance's fetch directory +// lowercaseified and $ changed to _ and reformatting for gas...pb Nov/95 + +//orig .MACRO $OSF_ALPHADEFS +//orig OSF_ALPHADEF_VER == 5 ; Flag the version number of this file. +//orig .ENDM +//orig .MACRO $OSF_PSDEF,$GBL +//orig $DEFINI OSFPS,$GBL +//orig;+ +//orig; PS Layout - PS +//orig; Loc Size name function +//orig; ------ ------ ----- ----------------------------------- +//orig; <0:2> 3 IPL Prio level +//orig; <3> 1 CM Current Mode +//orig;- + +#define osfps_v_mode 3 +#define osfps_m_mode (1< 32 PFN Page Frame Number +//orig; <31:16> 16 SOFT Bits reserved for software use +//orig; <15:14> 2 +//orig; <13> 1 UWE User write enable +//orig; <12> 1 KWE Kernel write enable +//orig; <11:10> 2 +//orig; <9> 1 URE User read enable +//orig; <8> 1 KRE Kernel read enable +//orig; <7:6> 2 RES Reserved SBZ +//orig; <5> 1 HPF Huge Page Flag +//orig; <4> 1 ASM Wild card address space number match +//orig; <3> 1 FOE Fault On execute +//orig; <2> 1 FOW Fault On Write +//orig; <1> 1 FOR Fault On Read +//orig; <0> 1 V valid bit +//orig;- + +//orig .MACRO _OSF_PTEDEF,_GBL +//orig _DEFINI OSFPTE,_GBL + +#define osfpte_v_pfn 32 +#define osfpte_m_soft (0xFFFF0000) +#define osfpte_v_soft 16 +#define osfpte_m_uwe (0x2000) +#define osfpte_v_uwe 13 +#define osfpte_m_kwe (0x1000) +#define osfpte_v_kwe 12 +#define osfpte_m_ure (0x0200) +#define osfpte_v_ure 9 +#define osfpte_m_kre (0x0100) +#define osfpte_v_kre 8 +#define osfpte_m_hpf (0x0020) +#define osfpte_v_hpf 5 +#define osfpte_m_asm (0x0010) +#define osfpte_v_asm 4 +#define osfpte_m_foe (0x0008) +#define osfpte_v_foe 3 +#define osfpte_m_fow (0x0004) +#define osfpte_v_fow 2 +#define osfpte_m_for (0x0002) +#define osfpte_v_for 1 +#define osfpte_m_v (0x0001) +#define osfpte_v_v 0 + +#define osfpte_m_ksegbits (osfpte_m_kre | osfpte_m_kwe | osfpte_m_v | osfpte_m_asm) +#define osfpte_m_prot (osfpte_m_ure+osfpte_m_uwe | osfpte_m_kre | osfpte_m_kwe) + +//orig _DEFEND OSFPTE,_GBL,DEF +//orig .ENDM + +//orig;+ +//orig; VA layout - symbol prefix VA_ +//orig; +//orig; Loc Size name function +//orig; ------ ------ ------- ----------------------------------- +//orig; <42:33> 10 SEG1 First seg table offset for mapping +//orig; <32:23> 10 SEG2 Second seg table offset for mapping +//orig; <22:13> 10 SEG3 Third seg table offset for mapping +//orig; <12:0> 13 OFFSET Byte within page +//orig;- +//orig .MACRO _OSF_VADEF,_GBL +//orig _DEFINI OSFVA,_GBL + +#define osfva_m_offset (0x000000001FFF) +#define osfva_v_offset 0 +#define osfva_m_seg3 (0x0000007FE000) +#define osfva_v_seg3 13 +#define osfva_m_seg2 (0x0001FF800000) +#define osfva_v_seg2 23 +#define osfva_m_seg1 (0x7FE00000000) +#define osfva_v_seg1 33 + +//orig _DEFEND OSFVA,_GBL,DEF +//orig .ENDM +//orig;+ +//orig; PRIVILEGED CONTEXT BLOCK (PCB) +//orig;- +//orig .MACRO _OSF_PCBDEF,_GBL +//orig _DEFINI OSFPCB,_GBL + +#define osfpcb_q_ksp (0x0000) +#define osfpcb_q_usp (0x0008) +#define osfpcb_q_Usp (0x0008) +#define osfpcb_q_mmptr (0x0010) +#define osfpcb_q_Mmptr (0x0010) +#define osfpcb_l_cc (0x0018) +#define osfpcb_l_asn (0x001C) +#define osfpcb_q_unique (0x0020) +#define osfpcb_q_fen (0x0028) +#define osfpcb_v_pme 62 + +//orig _DEFEND OSFPCB,_GBL,DEF +//orig .ENDM +//orig;+ +//orig; Stack Frame +//orig;- +//orig .MACRO _OSF_SFDEF,_GBL +//orig _DEFINI OSFSF,_GBL + +#define osfsf_ps (0x00) +#define osfsf_pc (0x08) +#define osfsf_gp (0x10) +#define osfsf_a0 (0x18) +#define osfsf_a1 (0x20) +#define osfsf_a2 (0x28) +#define osfsf_c_size (0x30) + +//orig _DEFEND OSFSF,_GBL,DEF +//orig .ENDM + +#endif diff --git a/system/alpha/h/ev5_paldef.h b/system/alpha/h/ev5_paldef.h new file mode 100644 index 000000000..5f9241b12 --- /dev/null +++ b/system/alpha/h/ev5_paldef.h @@ -0,0 +1,185 @@ +#ifndef EV5_PALDEF_INCLUDED +#define EV5_PALDEF_INCLUDED 1 + +// from ev5_paldef.mar from Lance's fetch directory...pb Nov/95 +// some entries have been superceeded by the more recent evt_defs.h + +// These are lower-caseified and have the $ signs (unnecessarily we now discover) removed. + +// Note that at the bottom of this file is the version of ev5_defs.mar +// which is more recent than the top part of the file and contains overlapping information...pb Nov/95 + +// .MACRO PALDEFS +// PALDEF_VER == 1 ; Flag the version number of this file. +// .ENDM +// +// +// .MACRO _HALT_CODES,_GBL +// _DEFINI HALT_CODES,_GBL + +#define hlt_c_reset 0 +#define hlt_c_hw_halt 1 +#define hlt_c_ksp_inval 2 +#define hlt_c_scbb_inval 3 +#define hlt_c_ptbr_inval 4 +#define hlt_c_sw_halt 5 +#define hlt_c_dbl_mchk 6 +#define hlt_c_mchk_from_pal 7 +#define hlt_c_start 32 +#define hlt_c_callback 33 +#define hlt_c_mpstart 34 +#define hlt_c_lfu_start 35 + +// halt codes above 255 reserved for platform specific errors +// _DEFEND HALT_CODES,_GBL,DEF +// .ENDM +// .MACRO _MCHK_CODES,_GBL +// _DEFINI MCHK_CODES,_GBL + +#define mchk_c_tperr (64<<1) +#define mchk_c_tcperr (65<<1) +#define mchk_c_herr (66<<1) +#define mchk_c_ecc_c (67<<1) +#define mchk_c_ecc_nc (68<<1) +#define mchk_c_unknown (69<<1) +#define mchk_c_cacksoft (70<<1) +#define mchk_c_bugcheck (71<<1) +#define mchk_c_os_bugcheck (72<<1) +#define mchk_c_dcperr (73<<1) +#define mchk_c_icperr (74<<1) +#define mchk_c_retryable_ird (75<<1) +#define mchk_c_proc_hrd_error (76<<1) +#define mchk_c_scperr (77<<1) +#define mchk_c_bcperr (78<<1) +//; mchk codes above 255 reserved for platform specific errors + + +#define mchk_c_read_nxm (256<<1) +#define mchk_c_sys_hrd_error (257<<1) +#define mchk_c_sys_ecc (258<<1) + +// _DEFEND MCHK_CODES,_GBL,DEF +// .ENDM + +// .MACRO _EV5_MM,_GBL +// _DEFINI _EV5_MM,_GBL + +#define page_seg_size_bits 10 +#define page_offset_size_bits 13 +#define page_size_bytes 8192 +#define va_size_bits 43 +#define pa_size_bits 45 + +// _DEFEND _EV5_MM,_GBL,DEF +// .ENDM + +// .MACRO _PALTEMP,_GBL +// _DEFINI _PALTEMP,_GBL + +// replaced by ev5_defs.h #define pt0 (0x140) +// replaced by ev5_defs.h #define pt1 (0x141) +// replaced by ev5_defs.h #define pt2 (0x142) +#define pt_entuna (0x142) +// replaced by ev5_defs.h #define pt3 (0x143) +#define pt_impure (0x143) +// replaced by ev5_defs.h #define pt4 (0x144) +// replaced by ev5_defs.h #define pt5 (0x145) +// replaced by ev5_defs.h #define pt6 (0x146) +// replaced by ev5_defs.h #define pt7 (0x147) +#define pt_entif (0x147) +// replaced by ev5_defs.h #define pt8 (0x148) +#define pt_intmask (0x148) +// replaced by ev5_defs.h #define pt9 (0x149) +#define pt_entsys (0x149) +#define pt_ps (0x149) +// replaced by ev5_defs.h #define pt10 (0x14a) +// replaced by ev5_defs.h #define pt11 (0x14b) +#define pt_trap (0x14b) +#define pt_entint (0x14b) +// replaced by ev5_defs.h #define pt12 (0x14c) +#define pt_entarith (0x14c) +// replaced by ev5_defs.h #define pt13 (0x14d) +#define pt_sys0 (0x14d) +// replaced by ev5_defs.h #define pt14 (0x14e) +#define pt_sys1 (0x14e) +// replaced by ev5_defs.h #define pt15 (0x14f) +#define pt_sys2 (0x14f) +// replaced by ev5_defs.h #define pt16 (0x150) +#define pt_whami (0x150) +#define pt_mces (0x150) +#define pt_misc (0x150) +// replaced by ev5_defs.h #define pt17 (0x151) +#define pt_scc (0x151) +#define pt_sysval (0x151) +// replaced by ev5_defs.h #define pt18 (0x152) +#define pt_prbr (0x152) +#define pt_usp (0x152) +// replaced by ev5_defs.h #define pt19 (0x153) +#define pt_ksp (0x153) +// replaced by ev5_defs.h #define pt20 (0x154) +#define pt_ptbr (0x154) +// replaced by ev5_defs.h #define pt21 (0x155) +#define pt_vptbr (0x155) +#define pt_entmm (0x155) +// replaced by ev5_defs.h #define pt22 (0x156) +#define pt_scbb (0x156) +#define pt_kgp (0x156) +// replaced by ev5_defs.h #define pt23 (0x157) +#define pt_pcbb (0x157) + + +#define pt_misc_v_switch 48 +#define pt_misc_v_cm 56 + +// _DEFEND _PALTEMP,_GBL,DEF +// .ENDM + +// .MACRO _OSF_MMCSR_DEF,_GBL +// _DEFINI OSFMMCSR,_GBL + +#define mmcsr_c_tnv 0 +#define mmcsr_c_acv 1 +#define mmcsr_c_for 2 +#define mmcsr_c_foe 3 +#define mmcsr_c_fow 4 + +// _DEFEND OSFMMCSR,_GBL,DEF +// .ENDM + +// .MACRO _MM_STAT_DEF,_GBL +// _DEFINI MMSTATDEF,_GBL + +#define mm_stat_m_opcode (0x3F) +#define mm_stat_m_ra (0x1F) +#define evx_opc_sync (0x18) +#define EVX_OPC_SYNC (0x18) +#define evx_opc_hw_ld (0x1B) + +// _DEFEND MMSTATDEF,_GBL,DEF +// .ENDM + +// .MACRO _OSF_A0_DEF,_GBL +// _DEFINI OSFA0DEF,_GBL + +#define osf_a0_bpt (0x0) +#define osf_a0_bugchk (0x1) +#define osf_a0_gentrap (0x2) +#define osf_a0_fen (0x3) +#define osf_a0_opdec (0x4) + +// _DEFEND OSFA0DEF,_GBL,DEF +// .ENDM + +// .MACRO _EV5_IPLDEF,_GBL +// _DEFINI EV5_IPLDEF,_GBL + +#define ipl_machine_check 31 +#define ipl_powerfail 30 +#define ipl_perf_count 29 +#define ipl_clock 22 +#define ipl_interprocessor 22 + +// _DEFEND EV5_IPLDEF,_GBL,DEF +// .ENDM + +#endif diff --git a/system/alpha/h/fromHudsonMacros.h b/system/alpha/h/fromHudsonMacros.h new file mode 100644 index 000000000..4b22d87ac --- /dev/null +++ b/system/alpha/h/fromHudsonMacros.h @@ -0,0 +1,145 @@ +#ifndef HUDSON_MACROS_LOADED +#define HUDSON_MACROS_LOADED 1 + +/* + * VID: [T1.2] PT: [Fri Apr 21 16:47:16 1995] SF: [macros.h] + * TI: [/sae_users/cruz/bin/vice -iplatform.s -l// -p# -DEB164 -h -m -aeb164 ] + */ +/* +***************************************************************************** +** * +** Copyright © 1993, 1994 * +** by Digital Equipment Corporation, Maynard, Massachusetts. * +** * +** All Rights Reserved * +** * +** Permission is hereby granted to use, copy, modify and distribute * +** this software and its documentation, in both source code and * +** object code form, and without fee, for the purpose of distribution * +** of this software or modifications of this software within products * +** incorporating an integrated circuit implementing Digital's AXP * +** architecture, regardless of the source of such integrated circuit, * +** provided that the above copyright notice and this permission notice * +** appear in all copies, and that the name of Digital Equipment * +** Corporation not be used in advertising or publicity pertaining to * +** distribution of the document or software without specific, written * +** prior permission. * +** * +** Digital Equipment Corporation disclaims all warranties and/or * +** guarantees with regard to this software, including all implied * +** warranties of fitness for a particular purpose and merchantability, * +** and makes no representations regarding the use of, or the results * +** of the use of, the software and documentation in terms of correctness, * +** accuracy, reliability, currentness or otherwise; and you rely on * +** the software, documentation and results solely at your own risk. * +** * +** AXP is a trademark of Digital Equipment Corporation. * +** * +***************************************************************************** +** +** FACILITY: +** +** DECchip 21164 PALcode +** +** MODULE: +** +** macros.h +** +** MODULE DESCRIPTION: +** +** DECchip 21164 PALcode macro definitions +** +** AUTHOR: ER +** +** CREATION DATE: 29-Nov-1993 +** +** $Id: fromHudsonMacros.h,v 1.1.1.1 1997/10/30 23:27:19 verghese Exp $ +** +** MODIFICATION HISTORY: +** +** $Log: fromHudsonMacros.h,v $ +** Revision 1.1.1.1 1997/10/30 23:27:19 verghese +** current 10/29/97 +** +** Revision 1.1 1995/11/18 01:46:23 boyle +** Initial revision +** +** Revision 1.5 1994/07/08 17:03:12 samberg +** Changes to support platform specific additions +** +** Revision 1.4 1994/05/20 19:24:19 ericr +** Moved STALL macro from osfpal.s to here +** Added LDLI macro +** +** Revision 1.3 1994/05/20 18:08:14 ericr +** Changed line comments to C++ style comment character +** +** Revision 1.2 1994/02/28 18:45:51 ericr +** Fixed EGORE related bugs +** +** Revision 1.1 1993/12/16 21:55:05 eric +** Initial revision +** +** +**-- +*/ + +#define STALL \ + mfpr r31, pt0 + +#define NOP \ + bis $31, $31, $31 + +/* +** Align code on an 8K byte page boundary. +*/ + +#define ALIGN_PAGE \ + .align 13 + +/* +** Align code on a 32 byte block boundary. +*/ + +#define ALIGN_BLOCK \ + .align 5 + +/* +** Align code on a quadword boundary. +*/ + +#define ALIGN_BRANCH \ + .align 3 + +/* +** Hardware vectors go in .text 0 sub-segment. +*/ + +#define HDW_VECTOR(offset) \ + . = offset + +/* +** Privileged CALL_PAL functions are in .text 1 sub-segment. +*/ + +#define CALL_PAL_PRIV(vector) \ + . = (PAL_CALL_PAL_PRIV_ENTRY+(vector<<6)) + +/* +** Unprivileged CALL_PAL functions are in .text 1 sub-segment, +** the privileged bit is removed from these vectors. +*/ + +#define CALL_PAL_UNPRIV(vector) \ + . = (PAL_CALL_PAL_UNPRIV_ENTRY+((vector&0x3F)<<6)) + +/* +** Implements a load "immediate" longword function +*/ +#define LDLI(reg,val) \ + ldah reg, ((val+0x8000) >> 16)(zero); \ + lda reg, (val&0xffff)(reg) + + + +#endif diff --git a/system/alpha/h/fromHudsonOsf.h b/system/alpha/h/fromHudsonOsf.h new file mode 100644 index 000000000..f9cb2f747 --- /dev/null +++ b/system/alpha/h/fromHudsonOsf.h @@ -0,0 +1,554 @@ +#ifndef FROMHUDSONOSF_INCLUDED +#define FROMHUDSONOSF_INCLUDED 1 +/* + * VID: [T1.2] PT: [Fri Apr 21 16:47:14 1995] SF: [osf.h] + * TI: [/sae_users/cruz/bin/vice -iplatform.s -l// -p# -DEB164 -h -m -aeb164 ] + */ +#define __OSF_LOADED 1 +/* +***************************************************************************** +** * +** Copyright © 1993, 1994 * +** by Digital Equipment Corporation, Maynard, Massachusetts. * +** * +** All Rights Reserved * +** * +** Permission is hereby granted to use, copy, modify and distribute * +** this software and its documentation, in both source code and * +** object code form, and without fee, for the purpose of distribution * +** of this software or modifications of this software within products * +** incorporating an integrated circuit implementing Digital's AXP * +** architecture, regardless of the source of such integrated circuit, * +** provided that the above copyright notice and this permission notice * +** appear in all copies, and that the name of Digital Equipment * +** Corporation not be used in advertising or publicity pertaining to * +** distribution of the document or software without specific, written * +** prior permission. * +** * +** Digital Equipment Corporation disclaims all warranties and/or * +** guarantees with regard to this software, including all implied * +** warranties of fitness for a particular purpose and merchantability, * +** and makes no representations regarding the use of, or the results * +** of the use of, the software and documentation in terms of correctness, * +** accuracy, reliability, currentness or otherwise; and you rely on * +** the software, documentation and results solely at your own risk. * +** * +** AXP is a trademark of Digital Equipment Corporation. * +** * +***************************************************************************** +** +** FACILITY: +** +** DECchip 21164 PALcode +** +** MODULE: +** +** osf.h +** +** MODULE DESCRIPTION: +** +** OSF/1 specific definitions +** +** AUTHOR: ER +** +** CREATION DATE: 24-Nov-1993 +** +** $Id: fromHudsonOsf.h,v 1.1.1.1 1997/10/30 23:27:19 verghese Exp $ +** +** MODIFICATION HISTORY: +** +** $Log: fromHudsonOsf.h,v $ +** Revision 1.1.1.1 1997/10/30 23:27:19 verghese +** current 10/29/97 +** +** Revision 1.1 1995/11/18 01:46:31 boyle +** Initial revision +** +** Revision 1.11 1995/04/21 02:06:30 fdh +** Replaced C++ style comments with Standard C style comments. +** +** Revision 1.10 1994/09/26 14:17:47 samberg +** Complete VICE work and EB164/SD164 breakout. +** +** Revision 1.9 1994/07/26 17:39:10 samberg +** Changes for SD164. +** +** Revision 1.8 1994/07/08 17:03:48 samberg +** Changes to support platform specific additions +** +** Revision 1.7 1994/05/20 19:23:51 ericr +** Moved STACK_FRAME macro from osfpal.s to here +** +** Revision 1.6 1994/05/20 18:08:19 ericr +** Changed line comments to C++ style comment character +** +** Revision 1.5 1994/01/11 18:43:33 ericr +** Removed PAL version/revision and size constants +** +** Revision 1.4 1994/01/05 16:22:32 ericr +** Added more SCB vector offsets and MCHK error code +** +** Revision 1.3 1994/01/03 19:35:40 ericr +** Derive mask definitions from field constants +** +** Revision 1.2 1993/12/22 20:43:01 eric +** Added mask definitions for MCES bits +** +** Revision 1.1 1993/12/16 21:55:05 eric +** Initial revision +** +** +**-- +*/ + +/* +** Seg0 and Seg1 Virtual Address (VA) Format +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <42:33> 10 SEG1 First level page table offset +** <32:23> 10 SEG2 Second level page table offset +** <22:13> 10 SEG3 Third level page table offset +** <12:00> 13 OFFSET Byte within page offset +*/ + +#define VA_V_SEG1 33 +#define VA_M_SEG1 (0x3FF< 32 PFN Page Frame Number +** <31:16> 16 SW Reserved for software +** <15:14> 2 RSV0 Reserved for hardware SBZ +** <13> 1 UWE User Write Enable +** <12> 1 KWE Kernel Write Enable +** <11:10> 2 RSV1 Reserved for hardware SBZ +** <9> 1 URE User Read Enable +** <8> 1 KRE Kernel Read Enable +** <7> 1 RSV2 Reserved for hardware SBZ +** <6:5> 2 GH Granularity Hint +** <4> 1 ASM Address Space Match +** <3> 1 FOE Fault On Execute +** <2> 1 FOW Fault On Write +** <1> 1 FOR Fault On Read +** <0> 1 V Valid +*/ + +#define PTE_V_PFN 32 +#define PTE_M_PFN 0xFFFFFFFF00000000 +#define PTE_V_SW 16 +#define PTE_M_SW 0x00000000FFFF0000 +#define PTE_V_UWE 13 +#define PTE_M_UWE (1< 1 CM Current Mode +** <2:0> 3 IPL Interrupt Priority Level +**/ + +#define PS_V_CM 3 +#define PS_M_CM (1< 1 MIP Machine check in progress +** <1> 1 SCE System correctable error in progress +** <2> 1 PCE Processor correctable error in progress +** <3> 1 DPC Disable PCE error reporting +** <4> 1 DSC Disable SCE error reporting +*/ + +#define MCES_V_MIP 0 +#define MCES_M_MIP (1< 8 ID Who-Am-I identifier +** <15:8> 1 SWAP Swap PALcode flag - character 'S' +*/ + +#define WHAMI_V_SWAP 8 +#define WHAMI_M_SWAP (1< 1 TST RW,0 Assert Test Status -** <38> 1 ISTA RO I-Cache BIST Status -** <37> 1 DBS RW,1 Debug Port Select -** <36> 1 FBD RW,0 Force Bad I-Cache Data Parity -** <35> 1 FBT RW,0 Force Bad I-Cache Tag Parity -** <34> 1 FMS RW,0 Force I-Cache Miss -** <33> 1 SLE RW,0 Enable Serial Line Interrupts -** <32> 1 CRDE RW,0 Enable Correctable Error Interrupts -** <30> 1 SDE RW,0 Enable PAL Shadow Registers -** <29:28> 2 SPE RW,0 Enable I-Stream Super Page Mode -** <27> 1 HWE RW,0 Enable PALRES Instrs in Kernel Mode -** <26> 1 FPE RW,0 Enable Floating Point Instructions -** <25> 1 TMD RW,0 Disable Ibox Timeout Counter -** <24> 1 TMM RW,0 Timeout Counter Mode -** -*/ - -#define ICSR_V_TST 39 -#define ICSR_M_TST (1< 1 TMT WO,1 Serial line transmit data -** -*/ - -#define SLXMIT_V_TMT 7 -#define SLXMIT_M_TMT (1< 1 RCV RO Serial line receive data -** -*/ - -#define SLRCV_V_RCV 6 -#define SLRCV_M_RCV (1< 1 TMR W1C Timeout reset error -** <12> 1 TPE W1C Tag parity error -** <11> 1 DPE W1C Data parity error -** -*/ - -#define ICPERR_V_TMR 13 -#define ICPERR_M_TMR (1< 1 IOV WA Integer overflow -** <15> 1 INE WA Inexact result -** <14> 1 UNF WA Underflow -** <13> 1 FOV WA Overflow -** <12> 1 DZE WA Division by zero -** <11> 1 INV WA Invalid operation -** <10> 1 SWC WA Software completion -** -*/ - -#define EXC_V_IOV 16 -#define EXC_M_IOV (1< 1 SLC W1C Clear Serial Line interrupt -** <32> 1 CRDC W1C Clear Correctable Read Data interrupt -** <29> 1 PC2C W1C Clear Performance Counter 2 interrupt -** <28> 1 PC1C W1C Clear Performance Counter 1 interrupt -** <27> 1 PC0C W1C Clear Performance Counter 0 interrupt -** -*/ - -#define HWINT_V_SLC 33 -#define HWINT_M_SLC (1< 1 HLT RO External Halt interrupt -** <33> 1 SLI RO Serial Line interrupt -** <32> 1 CRD RO Correctable ECC errors -** <31> 1 MCK RO System Machine Check -** <30> 1 PFL RO Power Fail -** <29> 1 PC2 RO Performance Counter 2 interrupt -** <28> 1 PC1 RO Performance Counter 1 interrupt -** <27> 1 PC0 RO Performance Counter 0 interrupt -** <23> 1 I23 RO External Hardware interrupt -** <22> 1 I22 RO External Hardware interrupt -** <21> 1 I21 RO External Hardware interrupt -** <20> 1 I20 RO External Hardware interrupt -** <19> 1 ATR RO Async. System Trap request -** <18:4> 15 SIRR RO,0 Software Interrupt request -** <3:0> 4 ASTRR RO Async. System Trap request (USEK) -** -**/ - -#define ISR_V_HLT 34 -#define ISR_M_HLT (1< 6 OPCODE RO Opcode of faulting instruction -** <10:06> 5 RA RO Ra field of faulting instruction -** <5> 1 BAD_VA RO Bad virtual address -** <4> 1 DTB_MISS RO Reference resulted in DTB miss -** <3> 1 FOW RO Fault on write -** <2> 1 FOR RO Fault on read -** <1> 1 ACV RO Access violation -** <0> 1 WR RO Reference type -** -*/ - -#define MMSTAT_V_OPC 11 -#define MMSTAT_M_OPC (0x3F< 1 DBG1 RW,0 Mbox Debug Packet Select -** <4> 1 E_BE RW,0 Ebox Big Endian mode enable -** <3> 1 DBG0 RW,0 Debug Test Select -** <2:1> 2 SP RW,0 Superpage mode enable -** <0> 1 M_BE RW,0 Mbox Big Endian mode enable -** -*/ - -#define MCSR_V_DBG1 5 -#define MCSR_M_DBG1 (1< 1 TP1 RO Dcache bank 1 tag parity error -** <4> 1 TP0 RO Dcache bank 0 tag parity error -** <3> 1 DP1 RO Dcache bank 1 data parity error -** <2> 1 DP0 RO Dcache bank 0 data parity error -** <1> 1 LOCK W1C Locks/clears bits <5:2> -** <0> 1 SEO W1C Second Dcache parity error occurred -** -*/ - -#define DCPERR_V_TP1 5 -#define DCPERR_M_TP1 (1< 1 DOA RO Hardware Dcache Disable -** <3> 1 PERR_DIS RW,0 Disable Dcache Parity Error reporting -** <2> 1 BAD_DP RW,0 Force Dcache data bad parity -** <1> 1 FHIT RW,0 Force Dcache hit -** <0> 1 ENA RW,0 Software Dcache Enable -** -*/ - -#define DC_V_DOA 4 -#define DC_M_DOA (1< 1 WB RO,0 If set, pending WB request -** <6> 1 DREAD RO,0 If set, pending D-read request -** -*/ - -#define MAF_V_WB_PENDING 7 -#define MAF_M_WB_PENDING (1< 3 SET_EN RW,1 Set enable -** <12> 1 BLK_SIZE RW,1 Scache/Bcache block size select -** <11:08> 4 FB_DP RW,0 Force bad data parity -** <07:02> 6 TAG_STAT RW Tag status and parity -** <1> 1 FLUSH RW,0 If set, clear all tag valid bits -** <0> 1 FHIT RW,0 Force hits -** -*/ - -#define SC_V_SET_EN 13 -#define SC_M_SET_EN (7< 1 DIS_VIC_BUF WO,0 Disable Scache victim buffer -** <26> 1 DIS_BAF_BYP WO,0 Disable speculative Bcache reads -** <25> 1 DBG_MUX_SEL WO,0 Debug MUX select -** <24:19> 6 PM_MUX_SEL WO,0 Performance counter MUX select -** <18:17> 2 BC_WAVE WO,0 Number of cycles of wave pipelining -** <16> 1 TL_PIPE_LATCH WO,0 Pipe system control pins -** <15> 1 EI_DIS_ERR WO,1 Disable ECC (parity) error -** <14:13> 2 BC_BAD_DAT WO,0 Force bad data -** <12:08> 5 BC_TAG_STAT WO Bcache tag status and parity -** <7> 1 BC_FHIT WO,0 Bcache force hit -** <6> 1 EI_ECC WO,1 ECC or byte parity mode -** <5> 1 VTM_FIRST WO,1 Drive out victim block address first -** <4> 1 CORR_FILL_DAT WO,1 Correct fill data -** <3> 1 EI_CMD_GRP3 WO,0 Drive MB command to external pins -** <2> 1 EI_CMD_GRP2 WO,0 Drive LOCK & SET_DIRTY to ext. pins -** <1> 1 ALLOC_CYC WO,0 Allocate cycle for non-cached LDs. -** <0> 1 BC_ENA W0,0 Bcache enable -** -*/ -#define BC_V_DIS_SC_VIC_BUF 27 -#define BC_M_DIS_SC_VIC_BUF (1<>1) -/* -** -** Bcache Configuration Register (BC_CONFIG) Bit Summary -** -** Extent Size Name Type Function -** ------ ---- ---- ---- --------------------------------- -** <35:29> 7 RSVD WO Reserved - Must Be Zero -** <28:20> 9 WE_CTL WO,0 Bcache write enable control -** <19:19> 1 RSVD WO,0 Reserved - Must Be Zero -** <18:16> 3 WE_OFF WO,1 Bcache fill write enable pulse offset -** <15:15> 1 RSVD WO,0 Reserved - Must Be Zero -** <14:12> 3 RD_WR_SPC WO,7 Bcache private read/write spacing -** <11:08> 4 WR_SPD WO,4 Bcache write speed in CPU cycles -** <07:04> 4 RD_SPD WO,4 Bcache read speed in CPU cycles -** <03:03> 1 RSVD WO,0 Reserved - Must Be Zero -** <02:00> 3 SIZE WO,1 Bcache size -*/ -#define BC_V_WE_CTL 20 -#define BC_M_WE_CTL (0x1FF< = 1. -*/ - -#define p0 r8 /* ITB/DTB Miss Scratch */ -#define p1 r9 /* ITB/DTB Miss Scratch */ -#define p2 r10 /* ITB/DTB Miss Scratch */ -#define p3 r11 -#define ps r11 /* Processor Status */ -#define p4 r12 /* Local Scratch */ -#define p5 r13 /* Local Scratch */ -#define p6 r14 /* Local Scratch */ -#define p7 r25 /* Local Scratch */ - -/* -** SRM Defined State Definitions: -*/ - -/* -** This table is an accounting of the DECchip 21164 storage used to -** implement the SRM defined state for OSF/1. -** -** IPR Name Internal Storage -** -------- ---------------- -** Processor Status ps, dtbCm, ipl, r11 -** Program Counter Ibox -** Interrupt Entry ptEntInt -** Arith Trap Entry ptEntArith -** MM Fault Entry ptEntMM -** Unaligned Access Entry ptEntUna -** Instruction Fault Entry ptEntIF -** Call System Entry ptEntSys -** User Stack Pointer ptUsp -** Kernel Stack Pointer ptKsp -** Kernel Global Pointer ptKgp -** System Value ptSysVal -** Page Table Base Register ptPtbr -** Virtual Page Table Base iVptBr, mVptBr -** Process Control Block Base ptPcbb -** Address Space Number itbAsn, dtbAsn -** Cycle Counter cc, ccCtl -** Float Point Enable icsr -** Lock Flag Cbox/System -** Unique PCB -** Who-Am-I ptWhami -*/ - -#define ptEntUna pt2 /* Unaligned Access Dispatch Entry */ -#define ptImpure pt3 /* Pointer To PAL Scratch Area */ -#define ptEntIF pt7 /* Instruction Fault Dispatch Entry */ -#define ptIntMask pt8 /* Interrupt Enable Mask */ -#define ptEntSys pt9 /* Call System Dispatch Entry */ -#define ptTrap pt11 -#define ptEntInt pt11 /* Hardware Interrupt Dispatch Entry */ -#define ptEntArith pt12 /* Arithmetic Trap Dispatch Entry */ -#if defined(KDEBUG) -#define ptEntDbg pt13 /* Kernel Debugger Dispatch Entry */ -#endif /* KDEBUG */ -#define ptMisc pt16 /* Miscellaneous Flags */ -#define ptWhami pt16 /* Who-Am-I Register Pt16<15:8> */ -#define ptMces pt16 /* Machine Check Error Summary Pt16<4:0> */ -#define ptSysVal pt17 /* Per-Processor System Value */ -#define ptUsp pt18 /* User Stack Pointer */ -#define ptKsp pt19 /* Kernel Stack Pointer */ -#define ptPtbr pt20 /* Page Table Base Register */ -#define ptEntMM pt21 /* MM Fault Dispatch Entry */ -#define ptKgp pt22 /* Kernel Global Pointer */ -#define ptPcbb pt23 /* Process Control Block Base */ - -/* -** -** Miscellaneous PAL State Flags (ptMisc) Bit Summary -** -** Extent Size Name Function -** ------ ---- ---- --------------------------------- -** <55:48> 8 SWAP Swap PALcode flag -- character 'S' -** <47:32> 16 MCHK Machine Check Error code -** <31:16> 16 SCB System Control Block vector -** <15:08> 8 WHAMI Who-Am-I identifier -** <04:00> 5 MCES Machine Check Error Summary bits -** -*/ - -#define PT16_V_MCES 0 -#define PT16_V_WHAMI 8 -#define PT16_V_SCB 16 -#define PT16_V_MCHK 32 -#define PT16_V_SWAP 48 - diff --git a/system/alpha/palcode/dc21164FromGasSources.h b/system/alpha/palcode/dc21164FromGasSources.h deleted file mode 100644 index 9b3389269..000000000 --- a/system/alpha/palcode/dc21164FromGasSources.h +++ /dev/null @@ -1,965 +0,0 @@ -#ifndef DC21164FROMGASSOURCES_INCLUDED -#define DC21164FROMGASSOURCES_INCLUDED 1 - -/* -***************************************************************************** -** * -** Copyright © 1993, 1994 * -** by Digital Equipment Corporation, Maynard, Massachusetts. * -** * -** All Rights Reserved * -** * -** Permission is hereby granted to use, copy, modify and distribute * -** this software and its documentation, in both source code and * -** object code form, and without fee, for the purpose of distribution * -** of this software or modifications of this software within products * -** incorporating an integrated circuit implementing Digital's AXP * -** architecture, regardless of the source of such integrated circuit, * -** provided that the above copyright notice and this permission notice * -** appear in all copies, and that the name of Digital Equipment * -** Corporation not be used in advertising or publicity pertaining to * -** distribution of the document or software without specific, written * -** prior permission. * -** * -** Digital Equipment Corporation disclaims all warranties and/or * -** guarantees with regard to this software, including all implied * -** warranties of fitness for a particular purpose and merchantability, * -** and makes no representations regarding the use of, or the results * -** of the use of, the software and documentation in terms of correctness, * -** accuracy, reliability, currentness or otherwise; and you rely on * -** the software, documentation and results solely at your own risk. * -** * -** AXP is a trademark of Digital Equipment Corporation. * -** * -***************************************************************************** -** -** FACILITY: -** -** DECchip 21164 PALcode -** -** MODULE: -** -** dc21164.h -** -** MODULE DESCRIPTION: -** -** DECchip 21164 specific definitions -** -** AUTHOR: ER -** -** CREATION DATE: 24-Nov-1993 -** -** $Id: dc21164FromGasSources.h,v 1.1.1.1 1997/10/30 23:27:19 verghese Exp $ -** -** MODIFICATION HISTORY: -** -** $Log: dc21164FromGasSources.h,v $ -** Revision 1.1.1.1 1997/10/30 23:27:19 verghese -** current 10/29/97 -** -** Revision 1.1 1995/11/18 01:45:46 boyle -** Initial revision -** -** Revision 1.15 1995/04/21 02:06:30 fdh -** Replaced C++ style comments with Standard C style comments. -** -** Revision 1.14 1995/03/20 14:55:23 samberg -** Add flushIc to make Roger Cruz's life easier. -** -** Revision 1.13 1994/12/14 15:52:48 samberg -** Add slXmit and slRcv bit definitions -** -** Revision 1.12 1994/09/07 15:43:49 samberg -** Changes for Makefile.vpp, take out OSF definition -** -** Revision 1.11 1994/07/26 17:38:35 samberg -** Changes for SD164. -** -** Revision 1.10 1994/07/08 17:02:12 samberg -** Changes to support platform specific additions -** -** Revision 1.8 1994/05/31 15:49:21 ericr -** Moved ptKdebug from pt10 to pt13; pt10 is used in MCHK flows -** -** Revision 1.7 1994/05/26 19:29:51 ericr -** Added BC_CONFIG definitions -** -** Revision 1.6 1994/05/25 14:27:25 ericr -** Added physical bit to ldq_lp and stq_cp macros -** -** Revision 1.5 1994/05/20 18:07:50 ericr -** Changed line comments to C++ style comment character -** -** Revision 1.4 1994/01/17 21:46:54 ericr -** Added floating point register definitions -** -** Revision 1.3 1994/01/03 19:31:49 ericr -** Added cache parity error status register definitions -** -** Revision 1.2 1993/12/22 20:42:35 eric -** Added ptTrap, ptMisc and flag definitions -** Added PAL shadow regsiter definitions -** -** Revision 1.1 1993/12/16 21:55:05 eric -** Initial revision -** -** -**-- -*/ - - -/* -** -** INTERNAL PROCESSOR REGISTER DEFINITIONS -** -** The internal processor register definitions below are annotated -** with one of the following symbols: -** -** RW - The register may be read and written -** RO - The register may only be read -** WO - The register may only be written -** -** For RO and WO registers, all bits and fields within the register are -** also read-only or write-only. For RW registers, each bit or field -** within the register is annotated with one of the following: -** -** RW - The bit/field may be read and written -** RO - The bit/field may be read; writes are ignored -** WO - The bit/field may be written; reads return UNPREDICTABLE -** WZ - The bit/field may be written; reads return a zero value -** W0C - The bit/field may be read; write-zero-to-clear -** W1C - The bit/field may be read; write-one-to-clear -** WA - The bit/field may be read; write-anything-to-clear -** RC - The bit/field may be read, causing state to clear; -** writes are ignored -** -*/ - - -/* -** -** Ibox IPR Definitions: -** -*/ - -// replaced by ev5_defs.h #define isr 0x100 /* RO - Interrupt Summary */ -#define itbTag 0x101 /* WO - ITB Tag */ -#define itbPte 0x102 /* RW - ITB Page Table Entry */ -#define itbAsn 0x103 /* RW - ITB Address Space Number */ -#define itbPteTemp 0x104 /* RO - ITB Page Table Entry Temporary */ -#define itbIa 0x105 /* WO - ITB Invalidate All */ -#define itbIap 0x106 /* WO - ITB Invalidate All Process */ -#define itbIs 0x107 /* WO - ITB Invalidate Single */ -// replaced by ev5_defs.h #define sirr 0x108 /* RW - Software Interrupt Request */ -// replaced by ev5_defs.h #define astrr 0x109 /* RW - Async. System Trap Request */ -// replaced by ev5_defs.h #define aster 0x10A /* RW - Async. System Trap Enable */ -#define excAddr 0x10B /* RW - Exception Address */ -#define excSum 0x10C /* RW - Exception Summary */ -#define excMask 0x10D /* RO - Exception Mask */ -#define palBase 0x10E /* RW - PAL Base */ -#define ips 0x10F /* RW - Processor Status */ -// replaced by ev5_defs.h #define ipl 0x110 /* RW - Interrupt Priority Level */ -#define intId 0x111 /* RO - Interrupt ID */ -#define iFaultVaForm 0x112 /* RO - Formatted Faulting VA */ -#define iVptBr 0x113 /* RW - I-Stream Virtual Page Table Base */ -#define hwIntClr 0x115 /* WO - Hardware Interrupt Clear */ -#define slXmit 0x116 /* WO - Serial Line Transmit */ -#define slRcv 0x117 /* RO - Serial Line Receive */ -// replaced by ev5_defs.h #define icsr 0x118 /* RW - Ibox Control/Status */ -#define icFlush 0x119 /* WO - I-Cache Flush Control */ -#define flushIc 0x119 /* WO - I-Cache Flush Control (DC21064 Symbol) */ -#define icPerr 0x11A /* RW - I-Cache Parity Error Status */ -#define PmCtr 0x11C /* RW - Performance Counter */ - -/* -** -** Ibox Control/Status Register (ICSR) Bit Summary -** -** Extent Size Name Type Function -** ------ ---- ---- ---- ------------------------------------ -** <39> 1 TST RW,0 Assert Test Status -** <38> 1 ISTA RO I-Cache BIST Status -** <37> 1 DBS RW,1 Debug Port Select -** <36> 1 FBD RW,0 Force Bad I-Cache Data Parity -** <35> 1 FBT RW,0 Force Bad I-Cache Tag Parity -** <34> 1 FMS RW,0 Force I-Cache Miss -** <33> 1 SLE RW,0 Enable Serial Line Interrupts -** <32> 1 CRDE RW,0 Enable Correctable Error Interrupts -** <30> 1 SDE RW,0 Enable PAL Shadow Registers -** <29:28> 2 SPE RW,0 Enable I-Stream Super Page Mode -** <27> 1 HWE RW,0 Enable PALRES Instrs in Kernel Mode -** <26> 1 FPE RW,0 Enable Floating Point Instructions -** <25> 1 TMD RW,0 Disable Ibox Timeout Counter -** <24> 1 TMM RW,0 Timeout Counter Mode -** -*/ - -#define ICSR_V_TST 39 -#define ICSR_M_TST (1< 1 TMT WO,1 Serial line transmit data -** -*/ - -#define SLXMIT_V_TMT 7 -#define SLXMIT_M_TMT (1< 1 RCV RO Serial line receive data -** -*/ - -#define SLRCV_V_RCV 6 -#define SLRCV_M_RCV (1< 1 TMR W1C Timeout reset error -** <12> 1 TPE W1C Tag parity error -** <11> 1 DPE W1C Data parity error -** -*/ - -#define ICPERR_V_TMR 13 -#define ICPERR_M_TMR (1< 1 IOV WA Integer overflow -** <15> 1 INE WA Inexact result -** <14> 1 UNF WA Underflow -** <13> 1 FOV WA Overflow -** <12> 1 DZE WA Division by zero -** <11> 1 INV WA Invalid operation -** <10> 1 SWC WA Software completion -** -*/ - -#define EXC_V_IOV 16 -#define EXC_M_IOV (1< 1 SLC W1C Clear Serial Line interrupt -** <32> 1 CRDC W1C Clear Correctable Read Data interrupt -** <29> 1 PC2C W1C Clear Performance Counter 2 interrupt -** <28> 1 PC1C W1C Clear Performance Counter 1 interrupt -** <27> 1 PC0C W1C Clear Performance Counter 0 interrupt -** -*/ - -#define HWINT_V_SLC 33 -#define HWINT_M_SLC (1< 1 HLT RO External Halt interrupt -** <33> 1 SLI RO Serial Line interrupt -** <32> 1 CRD RO Correctable ECC errors -** <31> 1 MCK RO System Machine Check -** <30> 1 PFL RO Power Fail -** <29> 1 PC2 RO Performance Counter 2 interrupt -** <28> 1 PC1 RO Performance Counter 1 interrupt -** <27> 1 PC0 RO Performance Counter 0 interrupt -** <23> 1 I23 RO External Hardware interrupt -** <22> 1 I22 RO External Hardware interrupt -** <21> 1 I21 RO External Hardware interrupt -** <20> 1 I20 RO External Hardware interrupt -** <19> 1 ATR RO Async. System Trap request -** <18:4> 15 SIRR RO,0 Software Interrupt request -** <3:0> 4 ASTRR RO Async. System Trap request (USEK) -** -**/ - -#define ISR_V_HLT 34 -#define ISR_M_HLT (1< 6 OPCODE RO Opcode of faulting instruction -** <10:06> 5 RA RO Ra field of faulting instruction -** <5> 1 BAD_VA RO Bad virtual address -** <4> 1 DTB_MISS RO Reference resulted in DTB miss -** <3> 1 FOW RO Fault on write -** <2> 1 FOR RO Fault on read -** <1> 1 ACV RO Access violation -** <0> 1 WR RO Reference type -** -*/ - -#define MMSTAT_V_OPC 11 -#define MMSTAT_M_OPC (0x3F< 1 DBG1 RW,0 Mbox Debug Packet Select -** <4> 1 E_BE RW,0 Ebox Big Endian mode enable -** <3> 1 DBG0 RW,0 Debug Test Select -** <2:1> 2 SP RW,0 Superpage mode enable -** <0> 1 M_BE RW,0 Mbox Big Endian mode enable -** -*/ - -#define MCSR_V_DBG1 5 -#define MCSR_M_DBG1 (1< 1 TP1 RO Dcache bank 1 tag parity error -** <4> 1 TP0 RO Dcache bank 0 tag parity error -** <3> 1 DP1 RO Dcache bank 1 data parity error -** <2> 1 DP0 RO Dcache bank 0 data parity error -** <1> 1 LOCK W1C Locks/clears bits <5:2> -** <0> 1 SEO W1C Second Dcache parity error occurred -** -*/ - -#define DCPERR_V_TP1 5 -#define DCPERR_M_TP1 (1< 1 DOA RO Hardware Dcache Disable -** <3> 1 PERR_DIS RW,0 Disable Dcache Parity Error reporting -** <2> 1 BAD_DP RW,0 Force Dcache data bad parity -** <1> 1 FHIT RW,0 Force Dcache hit -** <0> 1 ENA RW,0 Software Dcache Enable -** -*/ - -#define DC_V_DOA 4 -#define DC_M_DOA (1< 1 WB RO,0 If set, pending WB request -** <6> 1 DREAD RO,0 If set, pending D-read request -** -*/ - -#define MAF_V_WB_PENDING 7 -#define MAF_M_WB_PENDING (1< 3 SET_EN RW,1 Set enable -** <12> 1 BLK_SIZE RW,1 Scache/Bcache block size select -** <11:08> 4 FB_DP RW,0 Force bad data parity -** <07:02> 6 TAG_STAT RW Tag status and parity -** <1> 1 FLUSH RW,0 If set, clear all tag valid bits -** <0> 1 FHIT RW,0 Force hits -** -*/ - -#define SC_V_SET_EN 13 -#define SC_M_SET_EN (7< 1 DIS_VIC_BUF WO,0 Disable Scache victim buffer -** <26> 1 DIS_BAF_BYP WO,0 Disable speculative Bcache reads -** <25> 1 DBG_MUX_SEL WO,0 Debug MUX select -** <24:19> 6 PM_MUX_SEL WO,0 Performance counter MUX select -** <18:17> 2 BC_WAVE WO,0 Number of cycles of wave pipelining -** <16> 1 TL_PIPE_LATCH WO,0 Pipe system control pins -** <15> 1 EI_DIS_ERR WO,1 Disable ECC (parity) error -** <14:13> 2 BC_BAD_DAT WO,0 Force bad data -** <12:08> 5 BC_TAG_STAT WO Bcache tag status and parity -** <7> 1 BC_FHIT WO,0 Bcache force hit -** <6> 1 EI_ECC WO,1 ECC or byte parity mode -** <5> 1 VTM_FIRST WO,1 Drive out victim block address first -** <4> 1 CORR_FILL_DAT WO,1 Correct fill data -** <3> 1 EI_CMD_GRP3 WO,0 Drive MB command to external pins -** <2> 1 EI_CMD_GRP2 WO,0 Drive LOCK & SET_DIRTY to ext. pins -** <1> 1 ALLOC_CYC WO,0 Allocate cycle for non-cached LDs. -** <0> 1 BC_ENA W0,0 Bcache enable -** -*/ -#define BC_V_DIS_SC_VIC_BUF 27 -#define BC_M_DIS_SC_VIC_BUF (1<>1) -/* -** -** Bcache Configuration Register (BC_CONFIG) Bit Summary -** -** Extent Size Name Type Function -** ------ ---- ---- ---- --------------------------------- -** <35:29> 7 RSVD WO Reserved - Must Be Zero -** <28:20> 9 WE_CTL WO,0 Bcache write enable control -** <19:19> 1 RSVD WO,0 Reserved - Must Be Zero -** <18:16> 3 WE_OFF WO,1 Bcache fill write enable pulse offset -** <15:15> 1 RSVD WO,0 Reserved - Must Be Zero -** <14:12> 3 RD_WR_SPC WO,7 Bcache private read/write spacing -** <11:08> 4 WR_SPD WO,4 Bcache write speed in CPU cycles -** <07:04> 4 RD_SPD WO,4 Bcache read speed in CPU cycles -** <03:03> 1 RSVD WO,0 Reserved - Must Be Zero -** <02:00> 3 SIZE WO,1 Bcache size -*/ -#define BC_V_WE_CTL 20 -#define BC_M_WE_CTL (0x1FF< = 1. -*/ - -#define p0 r8 /* ITB/DTB Miss Scratch */ -#define p1 r9 /* ITB/DTB Miss Scratch */ -#define p2 r10 /* ITB/DTB Miss Scratch */ -#define p3 r11 -// #define ps r11 /* Processor Status */ -#define p4 r12 /* Local Scratch */ -#define p5 r13 /* Local Scratch */ -#define p6 r14 /* Local Scratch */ -#define p7 r25 /* Local Scratch */ - -/* -** SRM Defined State Definitions: -*/ - -/* -** This table is an accounting of the DECchip 21164 storage used to -** implement the SRM defined state for OSF/1. -** -** IPR Name Internal Storage -** -------- ---------------- -** Processor Status ps, dtbCm, ipl, r11 -** Program Counter Ibox -** Interrupt Entry ptEntInt -** Arith Trap Entry ptEntArith -** MM Fault Entry ptEntMM -** Unaligned Access Entry ptEntUna -** Instruction Fault Entry ptEntIF -** Call System Entry ptEntSys -** User Stack Pointer ptUsp -** Kernel Stack Pointer ptKsp -** Kernel Global Pointer ptKgp -** System Value ptSysVal -** Page Table Base Register ptPtbr -** Virtual Page Table Base iVptBr, mVptBr -** Process Control Block Base ptPcbb -** Address Space Number itbAsn, dtbAsn -** Cycle Counter cc, ccCtl -** Float Point Enable icsr -** Lock Flag Cbox/System -** Unique PCB -** Who-Am-I ptWhami -*/ - -#define ptEntUna pt2 /* Unaligned Access Dispatch Entry */ -#define ptImpure pt3 /* Pointer To PAL Scratch Area */ -#define ptEntIF pt7 /* Instruction Fault Dispatch Entry */ -#define ptIntMask pt8 /* Interrupt Enable Mask */ -#define ptEntSys pt9 /* Call System Dispatch Entry */ -#define ptTrap pt11 -#define ptEntInt pt11 /* Hardware Interrupt Dispatch Entry */ -#define ptEntArith pt12 /* Arithmetic Trap Dispatch Entry */ -#if defined(KDEBUG) -#define ptEntDbg pt13 /* Kernel Debugger Dispatch Entry */ -#endif /* KDEBUG */ -#define ptMisc pt16 /* Miscellaneous Flags */ -#define ptWhami pt16 /* Who-Am-I Register Pt16<15:8> */ -#define ptMces pt16 /* Machine Check Error Summary Pt16<4:0> */ -#define ptSysVal pt17 /* Per-Processor System Value */ -#define ptUsp pt18 /* User Stack Pointer */ -#define ptKsp pt19 /* Kernel Stack Pointer */ -#define ptPtbr pt20 /* Page Table Base Register */ -#define ptEntMM pt21 /* MM Fault Dispatch Entry */ -#define ptKgp pt22 /* Kernel Global Pointer */ -#define ptPcbb pt23 /* Process Control Block Base */ - -/* -** -** Miscellaneous PAL State Flags (ptMisc) Bit Summary -** -** Extent Size Name Function -** ------ ---- ---- --------------------------------- -** <55:48> 8 SWAP Swap PALcode flag -- character 'S' -** <47:32> 16 MCHK Machine Check Error code -** <31:16> 16 SCB System Control Block vector -** <15:08> 8 WHAMI Who-Am-I identifier -** <04:00> 5 MCES Machine Check Error Summary bits -** -*/ - -#define PT16_V_MCES 0 -#define PT16_V_WHAMI 8 -#define PT16_V_SCB 16 -#define PT16_V_MCHK 32 -#define PT16_V_SWAP 48 - -#endif /* DC21164FROMGASSOURCES_INCLUDED */ diff --git a/system/alpha/palcode/ev5_alpha_defs.h b/system/alpha/palcode/ev5_alpha_defs.h deleted file mode 100644 index 96769de04..000000000 --- a/system/alpha/palcode/ev5_alpha_defs.h +++ /dev/null @@ -1,323 +0,0 @@ -#ifndef EV5_ALPHA_DEFS_INCLUDED -#define EV5_ALPHA_DEFS_INCLUDED 1 - -// from ev5_alpha_defs.mar from Lance's fetch directory -// Lower-caseified and $ signs removed ... pb Nov/95 - -// .MACRO _ALPHADEFS -// ALPHADEF_VER == 6 ; Flag the version number of this file. -// .ENDM -// .MACRO _PSDEF,_GBL -// _DEFINI PS,_GBL -//;+ -//; PS Layout - PS -//; Loc Size name function -//; ------ ------ ______ ----------------------------------- -//; <31:29> 3 SA stack alignment -//; <31:13> 24 RES Reserved MBZ -//; <12:8> 5 IPL Priority level -//; <7> 1 VMM Virtual Mach Monitor -//; <6:5> 2 RES Reserved MBZ -//; <4:3> 2 CM Current Mode -//; <2> 1 IP Interrupt Pending -//; <1:0> 2 SW Software bits -//;- - -#define ps_v_sw 0 -#define ps_m_sw (3< 32 PFN Page Frame Number -//; <31:16> 16 SOFT Bits reserved for software use -//; <15> 1 UWE User write enable -//; <14> 1 SWE Super write enable -//; <13> 1 EWE Exec write enable -//; <12> 1 KWE Kernel write enable -//; <11> 1 URE User read enable -//; <10> 1 SRE Super read enable -//; <9> 1 ERE Exec read enable -//; <8> 1 KRE Kernel read enable -//; <7:6> 2 RES Reserved SBZ -//; <5> 1 HPF Huge Page Flag -//; <4> 1 ASM Wild card address space number match -//; <3> 1 FOE Fault On execute -//; <2> 1 FOW Fault On Write -//; <1> 1 FOR Fault On Read -//; <0> 1 V valid bit -//;- -// .MACRO _PTEDEF,_GBL -// _DEFINI PTE,_GBL - -#define pte_v_pfn 32 -#define pte_m_soft (0xFFFF0000) -#define pte_v_soft 16 -#define pte_m_uwe (0x8000) -#define pte_v_uwe 15 -#define pte_m_swe (0x4000) -#define pte_v_swe 14 -#define pte_m_ewe (0x2000) -#define pte_v_ewe 13 -#define pte_m_kwe (0x1000) -#define pte_v_kwe 12 -#define pte_m_ure (0x0800) -#define pte_v_ure 11 -#define pte_m_sre (0x0400) -#define pte_v_sre 10 -#define pte_m_ere (0x0200) -#define pte_v_ere 9 -#define pte_m_kre (0x0100) -#define pte_v_kre 8 -#define pte_m_hpf (0x0020) -#define pte_v_hpf 5 -#define pte_m_asm (0x0010) -#define pte_v_asm 4 -#define pte_m_foe (0x0008) -#define pte_v_foe 3 -#define pte_m_fow (0x0004) -#define pte_v_fow 2 -#define pte_m_for (0x0002) -#define pte_v_for 1 -#define pte_m_v (0x0001) -#define pte_v_v 0 - -// _DEFEND PTE,_GBL,DEF -// .ENDM -//;+ -//; VA layout - symbol prefix VA_ -//; -//; Loc Size name function -//; ------ ------ ------- ----------------------------------- -//; <42:33> 10 SEG1 First seg table offset for mapping -//; <32:23> 10 SEG2 Second seg table offset for mapping -//; <22:13> 10 SEG3 Third seg table offset for mapping -//; <12:0> 13 OFFSET Byte within page -//;- -// .MACRO _VADEF,_GBL -// _DEFINI VA,_GBL - -#define va_m_offset (0x000000001FFF) -#define va_v_offset 0 -#define va_m_seg3 (0x0000007FE000) -#define va_v_seg3 13 -#define va_m_seg2 (0x0001FF800000) -#define va_v_seg2 23 -#define va_m_seg1 (0x7FE00000000) -#define va_v_seg1 33 - -// _DEFEND VA,_GBL,DEF -// .ENDM -//;+ -//; PRIVILEGED CONTEXT BLOCK (PCB) -//;- -// .MACRO _PCBDEF,_GBL -// _DEFINI PCB,_GBL -#define pcb_q_ksp 0 -#define pcb_q_esp 8 -#define pcb_q_ssp 16 -#define pcb_q_usp 24 -#define pcb_q_ptbr 32 -#define pcb_q_asn 40 -#define pcb_q_ast 48 -#define pcb_q_fen 56 -#define pcb_q_cc 64 -#define pcb_q_unq 72 -#define pcb_q_sct 80 - -#define pcb_v_asten 0 -#define pcb_m_asten (0x0f< ; Software completion -// exs_v_inv <1> ; Ivalid operation -// exs_v_dze <2> ; Div by zero -// exs_v_fov <3> ; Floating point overflow -// exs_v_unf <4> ; Floating point underflow -// exs_v_ine <5> ; Floating point inexact -// exs_v_iov <6> ; Floating convert to integer overflow -#define exs_v_swc 0 -#define exs_v_inv 1 -#define exs_v_dze 2 -#define exs_v_fov 3 -#define exs_v_unf 4 -#define exs_v_ine 5 -#define exs_v_iov 6 - -#define exs_m_swc (1< ; machine check in progress -// mces_v_sce <1> ; system correctable error -// mces_v_pce <2> ; processor correctable error -// mces_v_dpc <3> ; disable reporting of processor correctable errors -// mces_v_dsc <4> ; disable reporting of system correctable errors -#define mces_v_mchk 0 -#define mces_v_sce 1 -#define mces_v_pce 2 -#define mces_v_dpc 3 -#define mces_v_dsc 4 - -#define mces_m_mchk (1<,..COL=<:> -// EV5$K_REVISION'..equ'34 -// In the definitions below, registers are annotated with one of the following -// symbols: -// -// RW - The register may be read and written -// RO - The register may only be read -// WO - The register may only be written -// -// For RO and WO registers, all bits and fields within the register are also -// read-only or write-only. For RW registers, each bit or field within -// the register is annotated with one of the following: -// -// RW - The bit/field may be read and written -// RO - The bit/field may be read; writes are ignored -// WO - The bit/field may be written; reads return an UNPREDICTABLE result. -// WZ - The bit/field may be written; reads return a 0 -// WC - The bit/field may be read; writes cause state to clear -// RC - The bit/field may be read, which also causes state to clear; writes are ignored -// Architecturally-defined (SRM) registers for EVMS -#define pt0 320 -#define pt1 321 -#define pt2 322 -#define pt3 323 -#define pt4 324 -#define pt5 325 -#define pt6 326 -#define pt7 327 -#define pt8 328 -#define pt9 329 -#define pt10 330 -#define pt11 331 -#define pt12 332 -#define pt13 333 -#define pt14 334 -#define pt15 335 -#define pt16 336 -#define pt17 337 -#define pt18 338 -#define pt19 339 -#define pt20 340 -#define pt21 341 -#define pt22 342 -#define pt23 343 -#define cbox_ipr_offset 16777200 -#define sc_ctl 168 -#define sc_stat 232 -#define sc_addr 392 -#define sc_addr_nm 392 -#define sc_addr_fhm 392 -#define bc_ctl 296 -#define bc_config 456 -#define ei_stat 360 -#define ei_addr 328 -#define fill_syn 104 -#define bc_tag_addr 264 -#define ld_lock 488 -#define aster 266 -#define astrr 265 -#define exc_addr 267 -#define exc_sum 268 -#define exc_mask 269 -#define hwint_clr 277 -#define ic_flush_ctl 281 -#define icperr_stat 282 -#define ic_perr_stat 282 -#define ic_row_map 283 -#define icsr 280 -#define ifault_va_form 274 -#define intid 273 -#define ipl 272 -#define isr 256 -#define itb_is 263 -#define itb_asn 259 -#define itb_ia 261 -#define itb_iap 262 -#define itb_pte 258 -#define itb_pte_temp 260 -#define itb_tag 257 -#define ivptbr 275 -#define pal_base 270 -#define pmctr 284 -// this is not the register ps .. pb #define ps 271 -#define sirr 264 -#define sl_txmit 278 -#define sl_rcv 279 -#define alt_mode 524 -#define cc 525 -#define cc_ctl 526 -#define dc_flush 528 -#define dcperr_stat 530 -#define dc_test_ctl 531 -#define dc_test_tag 532 -#define dc_test_tag_temp 533 -#define dtb_asn 512 -#define dtb_cm 513 -#define dtb_ia 522 -#define dtb_iap 521 -#define dtb_is 523 -#define dtb_pte 515 -#define dtb_pte_temp 516 -#define dtb_tag 514 -#define mcsr 527 -#define dc_mode 534 -#define maf_mode 535 -#define mm_stat 517 -#define mvptbr 520 -#define va 518 -#define va_form 519 -#define ev5_srm__ps 0 -#define ev5_srm__pc 0 -#define ev5_srm__asten 0 -#define ev5_srm__astsr 0 -#define ev5_srm__ipir 0 -#define ev5_srm__ipl 0 -#define ev5_srm__mces 0 -#define ev5_srm__pcbb 0 -#define ev5_srm__prbr 0 -#define ev5_srm__ptbr 0 -#define ev5_srm__scbb 0 -#define ev5_srm__sirr 0 -#define ev5_srm__sisr 0 -#define ev5_srm__tbchk 0 -#define ev5_srm__tb1a 0 -#define ev5_srm__tb1ap 0 -#define ev5_srm__tb1ad 0 -#define ev5_srm__tb1ai 0 -#define ev5_srm__tbis 0 -#define ev5_srm__ksp 0 -#define ev5_srm__esp 0 -#define ev5_srm__ssp 0 -#define ev5_srm__usp 0 -#define ev5_srm__vptb 0 -#define ev5_srm__whami 0 -#define ev5_srm__cc 0 -#define ev5_srm__unq 0 -// processor-specific iprs. -#define ev5__sc_ctl 168 -#define ev5__sc_stat 232 -#define ev5__sc_addr 392 -#define ev5__bc_ctl 296 -#define ev5__bc_config 456 -#define bc_config_k_size_1mb 1 -#define bc_config_k_size_2mb 2 -#define bc_config_k_size_4mb 3 -#define bc_config_k_size_8mb 4 -#define bc_config_k_size_16mb 5 -#define bc_config_k_size_32mb 6 -#define bc_config_k_size_64mb 7 -#define ev5__ei_stat 360 -#define ev5__ei_addr 328 -#define ev5__fill_syn 104 -#define ev5__bc_tag_addr 264 -#define ev5__aster 266 -#define ev5__astrr 265 -#define ev5__exc_addr 267 -#define exc_addr_v_pa 2 -#define exc_addr_s_pa 62 -#define ev5__exc_sum 268 -#define ev5__exc_mask 269 -#define ev5__hwint_clr 277 -#define ev5__ic_flush_ctl 281 -#define ev5__icperr_stat 282 -#define ev5__ic_perr_stat 282 -#define ev5__ic_row_map 283 -#define ev5__icsr 280 -#define ev5__ifault_va_form 274 -#define ev5__ifault_va_form_nt 274 -#define ifault_va_form_nt_v_vptb 30 -#define ifault_va_form_nt_s_vptb 34 -#define ev5__intid 273 -#define ev5__ipl 272 -#define ev5__itb_is 263 -#define ev5__itb_asn 259 -#define ev5__itb_ia 261 -#define ev5__itb_iap 262 -#define ev5__itb_pte 258 -#define ev5__itb_pte_temp 260 -#define ev5__itb_tag 257 -#define ev5__ivptbr 275 -#define ivptbr_v_vptb 30 -#define ivptbr_s_vptb 34 -#define ev5__pal_base 270 -#define ev5__pmctr 284 -#define ev5__ps 271 -#define ev5__isr 256 -#define ev5__sirr 264 -#define ev5__sl_txmit 278 -#define ev5__sl_rcv 279 -#define ev5__alt_mode 524 -#define ev5__cc 525 -#define ev5__cc_ctl 526 -#define ev5__dc_flush 528 -#define ev5__dcperr_stat 530 -#define ev5__dc_test_ctl 531 -#define ev5__dc_test_tag 532 -#define ev5__dc_test_tag_temp 533 -#define ev5__dtb_asn 512 -#define ev5__dtb_cm 513 -#define ev5__dtb_ia 522 -#define ev5__dtb_iap 521 -#define ev5__dtb_is 523 -#define ev5__dtb_pte 515 -#define ev5__dtb_pte_temp 516 -#define ev5__dtb_tag 514 -#define ev5__mcsr 527 -#define ev5__dc_mode 534 -#define ev5__maf_mode 535 -#define ev5__mm_stat 517 -#define ev5__mvptbr 520 -#define ev5__va 518 -#define ev5__va_form 519 -#define ev5__va_form_nt 519 -#define va_form_nt_s_va 19 -#define va_form_nt_v_vptb 30 -#define va_form_nt_s_vptb 34 -#define ev5s_ev5_def 10 -#define ev5_def 0 -// cbox registers. -#define sc_ctl_v_sc_fhit 0 -#define sc_ctl_v_sc_flush 1 -#define sc_ctl_s_sc_tag_stat 6 -#define sc_ctl_v_sc_tag_stat 2 -#define sc_ctl_s_sc_fb_dp 4 -#define sc_ctl_v_sc_fb_dp 8 -#define sc_ctl_v_sc_blk_size 12 -#define sc_ctl_s_sc_set_en 3 -#define sc_ctl_v_sc_set_en 13 -#define sc_ctl_s_sc_soft_repair 3 -#define sc_ctl_v_sc_soft_repair 16 -#define sc_stat_s_sc_tperr 3 -#define sc_stat_v_sc_tperr 0 -#define sc_stat_s_sc_dperr 8 -#define sc_stat_v_sc_dperr 3 -#define sc_stat_s_cbox_cmd 5 -#define sc_stat_v_cbox_cmd 11 -#define sc_stat_v_sc_scnd_err 16 -#define sc_addr_fhm_v_sc_tag_parity 4 -#define sc_addr_fhm_s_tag_stat_sb0 3 -#define sc_addr_fhm_v_tag_stat_sb0 5 -#define sc_addr_fhm_s_tag_stat_sb1 3 -#define sc_addr_fhm_v_tag_stat_sb1 8 -#define sc_addr_fhm_s_ow_mod0 2 -#define sc_addr_fhm_v_ow_mod0 11 -#define sc_addr_fhm_s_ow_mod1 2 -#define sc_addr_fhm_v_ow_mod1 13 -#define sc_addr_fhm_s_tag_lo 17 -#define sc_addr_fhm_v_tag_lo 15 -#define sc_addr_fhm_s_tag_hi 7 -#define sc_addr_fhm_v_tag_hi 32 -#define bc_ctl_v_bc_enabled 0 -#define bc_ctl_v_alloc_cyc 1 -#define bc_ctl_v_ei_opt_cmd 2 -#define bc_ctl_v_ei_opt_cmd_mb 3 -#define bc_ctl_v_corr_fill_dat 4 -#define bc_ctl_v_vtm_first 5 -#define bc_ctl_v_ei_ecc_or_parity 6 -#define bc_ctl_v_bc_fhit 7 -#define bc_ctl_s_bc_tag_stat 5 -#define bc_ctl_v_bc_tag_stat 8 -#define bc_ctl_s_bc_bad_dat 2 -#define bc_ctl_v_bc_bad_dat 13 -#define bc_ctl_v_ei_dis_err 15 -#define bc_ctl_v_tl_pipe_latch 16 -#define bc_ctl_s_bc_wave_pipe 2 -#define bc_ctl_v_bc_wave_pipe 17 -#define bc_ctl_s_pm_mux_sel 6 -#define bc_ctl_v_pm_mux_sel 19 -#define bc_ctl_v_dbg_mux_sel 25 -#define bc_ctl_v_dis_baf_byp 26 -#define bc_ctl_v_dis_sc_vic_buf 27 -#define bc_ctl_v_dis_sys_addr_par 28 -#define bc_ctl_v_read_dirty_cln_shr 29 -#define bc_ctl_v_write_read_bubble 30 -#define bc_ctl_v_bc_wave_pipe_2 31 -#define bc_ctl_v_auto_dack 32 -#define bc_ctl_v_dis_byte_word 33 -#define bc_ctl_v_stclk_delay 34 -#define bc_ctl_v_write_under_miss 35 -#define bc_config_s_bc_size 3 -#define bc_config_v_bc_size 0 -#define bc_config_s_bc_rd_spd 4 -#define bc_config_v_bc_rd_spd 4 -#define bc_config_s_bc_wr_spd 4 -#define bc_config_v_bc_wr_spd 8 -#define bc_config_s_bc_rd_wr_spc 3 -#define bc_config_v_bc_rd_wr_spc 12 -#define bc_config_s_fill_we_offset 3 -#define bc_config_v_fill_we_offset 16 -#define bc_config_s_bc_we_ctl 9 -#define bc_config_v_bc_we_ctl 20 -// cbox registers, continued -#define ei_stat_s_sys_id 4 -#define ei_stat_v_sys_id 24 -#define ei_stat_v_bc_tperr 28 -#define ei_stat_v_bc_tc_perr 29 -#define ei_stat_v_ei_es 30 -#define ei_stat_v_cor_ecc_err 31 -#define ei_stat_v_unc_ecc_err 32 -#define ei_stat_v_ei_par_err 33 -#define ei_stat_v_fil_ird 34 -#define ei_stat_v_seo_hrd_err 35 -// -#define bc_tag_addr_v_hit 12 -#define bc_tag_addr_v_tagctl_p 13 -#define bc_tag_addr_v_tagctl_d 14 -#define bc_tag_addr_v_tagctl_s 15 -#define bc_tag_addr_v_tagctl_v 16 -#define bc_tag_addr_v_tag_p 17 -#define bc_tag_addr_s_bc_tag 19 -#define bc_tag_addr_v_bc_tag 20 -// ibox and icache registers. -#define aster_v_kar 0 -#define aster_v_ear 1 -#define aster_v_sar 2 -#define aster_v_uar 3 -#define astrr_v_kar 0 -#define astrr_v_ear 1 -#define astrr_v_sar 2 -#define astrr_v_uar 3 -#define exc_addr_v_pal 0 -#define exc_sum_v_swc 10 -#define exc_sum_v_inv 11 -#define exc_sum_v_dze 12 -#define exc_sum_v_fov 13 -#define exc_sum_v_unf 14 -#define exc_sum_v_ine 15 -#define exc_sum_v_iov 16 -#define hwint_clr_v_pc0c 27 -#define hwint_clr_v_pc1c 28 -#define hwint_clr_v_pc2c 29 -#define hwint_clr_v_crdc 32 -#define hwint_clr_v_slc 33 -// ibox and icache registers, continued -#define icperr_stat_v_dpe 11 -#define icperr_stat_v_tpe 12 -#define icperr_stat_v_tmr 13 -#define ic_perr_stat_v_dpe 11 -#define ic_perr_stat_v_tpe 12 -#define ic_perr_stat_v_tmr 13 -#define icsr_v_pma 8 -#define icsr_v_pmp 9 -#define icsr_v_byt 17 -#define icsr_v_fmp 18 -#define icsr_v_im0 20 -#define icsr_v_im1 21 -#define icsr_v_im2 22 -#define icsr_v_im3 23 -#define icsr_v_tmm 24 -#define icsr_v_tmd 25 -#define icsr_v_fpe 26 -#define icsr_v_hwe 27 -#define icsr_s_spe 2 -#define icsr_v_spe 28 -#define icsr_v_sde 30 -#define icsr_v_crde 32 -#define icsr_v_sle 33 -#define icsr_v_fms 34 -#define icsr_v_fbt 35 -#define icsr_v_fbd 36 -#define icsr_v_dbs 37 -#define icsr_v_ista 38 -#define icsr_v_tst 39 -#define ifault_va_form_s_va 30 -#define ifault_va_form_v_va 3 -#define ifault_va_form_s_vptb 31 -#define ifault_va_form_v_vptb 33 -#define ifault_va_form_nt_s_va 19 -#define ifault_va_form_nt_v_va 3 -#define intid_s_intid 5 -#define intid_v_intid 0 -// ibox and icache registers, continued -#define ipl_s_ipl 5 -#define ipl_v_ipl 0 -#define itb_is_s_va 30 -#define itb_is_v_va 13 -#define itb_asn_s_asn 7 -#define itb_asn_v_asn 4 -#define itb_pte_v_asm 4 -#define itb_pte_s_gh 2 -#define itb_pte_v_gh 5 -#define itb_pte_v_kre 8 -#define itb_pte_v_ere 9 -#define itb_pte_v_sre 10 -#define itb_pte_v_ure 11 -#define itb_pte_s_pfn 27 -#define itb_pte_v_pfn 32 -#define itb_pte_temp_v_asm 13 -#define itb_pte_temp_v_kre 18 -#define itb_pte_temp_v_ere 19 -#define itb_pte_temp_v_sre 20 -#define itb_pte_temp_v_ure 21 -#define itb_pte_temp_s_gh 3 -#define itb_pte_temp_v_gh 29 -#define itb_pte_temp_s_pfn 27 -#define itb_pte_temp_v_pfn 32 -// ibox and icache registers, continued -#define itb_tag_s_va 30 -#define itb_tag_v_va 13 -#define pal_base_s_pal_base 26 -#define pal_base_v_pal_base 14 -#define pmctr_s_sel2 4 -#define pmctr_v_sel2 0 -#define pmctr_s_sel1 4 -#define pmctr_v_sel1 4 -#define pmctr_v_killk 8 -#define pmctr_v_killp 9 -#define pmctr_s_ctl2 2 -#define pmctr_v_ctl2 10 -#define pmctr_s_ctl1 2 -#define pmctr_v_ctl1 12 -#define pmctr_s_ctl0 2 -#define pmctr_v_ctl0 14 -#define pmctr_s_ctr2 14 -#define pmctr_v_ctr2 16 -#define pmctr_v_killu 30 -#define pmctr_v_sel0 31 -#define pmctr_s_ctr1 16 -#define pmctr_v_ctr1 32 -#define pmctr_s_ctr0 16 -#define pmctr_v_ctr0 48 -#define ps_v_cm0 3 -#define ps_v_cm1 4 -#define isr_s_astrr 4 -#define isr_v_astrr 0 -#define isr_s_sisr 15 -#define isr_v_sisr 4 -#define isr_v_atr 19 -#define isr_v_i20 20 -#define isr_v_i21 21 -#define isr_v_i22 22 -#define isr_v_i23 23 -#define isr_v_pc0 27 -#define isr_v_pc1 28 -#define isr_v_pc2 29 -#define isr_v_pfl 30 -#define isr_v_mck 31 -#define isr_v_crd 32 -#define isr_v_sli 33 -#define isr_v_hlt 34 -#define sirr_s_sirr 15 -#define sirr_v_sirr 4 -// ibox and icache registers, continued -#define sl_txmit_v_tmt 7 -#define sl_rcv_v_rcv 6 -// mbox and dcache registers. -#define alt_mode_v_am0 3 -#define alt_mode_v_am1 4 -#define cc_ctl_v_cc_ena 32 -#define dcperr_stat_v_seo 0 -#define dcperr_stat_v_lock 1 -#define dcperr_stat_v_dp0 2 -#define dcperr_stat_v_dp1 3 -#define dcperr_stat_v_tp0 4 -#define dcperr_stat_v_tp1 5 -// the following two registers are used exclusively for test and diagnostics. -// they should not be referenced in normal operation. -#define dc_test_ctl_v_bank0 0 -#define dc_test_ctl_v_bank1 1 -#define dc_test_ctl_v_fill_0 2 -#define dc_test_ctl_s_index 10 -#define dc_test_ctl_v_index 3 -#define dc_test_ctl_s_fill_1 19 -#define dc_test_ctl_v_fill_1 13 -#define dc_test_ctl_s_fill_2 32 -#define dc_test_ctl_v_fill_2 32 -// mbox and dcache registers, continued. -#define dc_test_tag_v_tag_par 2 -#define dc_test_tag_v_ow0 11 -#define dc_test_tag_v_ow1 12 -#define dc_test_tag_s_tag 26 -#define dc_test_tag_v_tag 13 -#define dc_test_tag_temp_v_tag_par 2 -#define dc_test_tag_temp_v_d0p0 3 -#define dc_test_tag_temp_v_d0p1 4 -#define dc_test_tag_temp_v_d1p0 5 -#define dc_test_tag_temp_v_d1p1 6 -#define dc_test_tag_temp_v_ow0 11 -#define dc_test_tag_temp_v_ow1 12 -#define dc_test_tag_temp_s_tag 26 -#define dc_test_tag_temp_v_tag 13 -#define dtb_asn_s_asn 7 -#define dtb_asn_v_asn 57 -#define dtb_cm_v_cm0 3 -#define dtb_cm_v_cm1 4 -#define dtbis_s_va0 30 -#define dtbis_v_va0 13 -#define dtb_pte_v_for 1 -#define dtb_pte_v_fow 2 -#define dtb_pte_v_asm 4 -#define dtb_pte_s_gh 2 -#define dtb_pte_v_gh 5 -#define dtb_pte_v_kre 8 -#define dtb_pte_v_ere 9 -#define dtb_pte_v_sre 10 -#define dtb_pte_v_ure 11 -#define dtb_pte_v_kwe 12 -#define dtb_pte_v_ewe 13 -#define dtb_pte_v_swe 14 -#define dtb_pte_v_uwe 15 -#define dtb_pte_s_pfn 27 -#define dtb_pte_v_pfn 32 -// mbox and dcache registers, continued. -#define dtb_pte_temp_v_for 0 -#define dtb_pte_temp_v_fow 1 -#define dtb_pte_temp_v_kre 2 -#define dtb_pte_temp_v_ere 3 -#define dtb_pte_temp_v_sre 4 -#define dtb_pte_temp_v_ure 5 -#define dtb_pte_temp_v_kwe 6 -#define dtb_pte_temp_v_ewe 7 -#define dtb_pte_temp_v_swe 8 -#define dtb_pte_temp_v_uwe 9 -#define dtb_pte_temp_v_asm 10 -#define dtb_pte_temp_s_fill_0 2 -#define dtb_pte_temp_v_fill_0 11 -#define dtb_pte_temp_s_pfn 27 -#define dtb_pte_temp_v_pfn 13 -#define dtb_tag_s_va 30 -#define dtb_tag_v_va 13 -// most mcsr bits are used for testability and diagnostics only. -// for normal operation, they will be supported in the following configuration: -// split_dcache = 1, maf_nomerge = 0, wb_flush_always = 0, wb_nomerge = 0, -// dc_ena<1:0> = 1, dc_fhit = 0, dc_bad_parity = 0 -#define mcsr_v_big_endian 0 -#define mcsr_v_sp0 1 -#define mcsr_v_sp1 2 -#define mcsr_v_mbox_sel 3 -#define mcsr_v_e_big_endian 4 -#define mcsr_v_dbg_packet_sel 5 -#define dc_mode_v_dc_ena 0 -#define dc_mode_v_dc_fhit 1 -#define dc_mode_v_dc_bad_parity 2 -#define dc_mode_v_dc_perr_dis 3 -#define dc_mode_v_dc_doa 4 -#define maf_mode_v_maf_nomerge 0 -#define maf_mode_v_wb_flush_always 1 -#define maf_mode_v_wb_nomerge 2 -#define maf_mode_v_io_nomerge 3 -#define maf_mode_v_wb_cnt_disable 4 -#define maf_mode_v_maf_arb_disable 5 -#define maf_mode_v_dread_pending 6 -#define maf_mode_v_wb_pending 7 -// mbox and dcache registers, continued. -#define mm_stat_v_wr 0 -#define mm_stat_v_acv 1 -#define mm_stat_v_for 2 -#define mm_stat_v_fow 3 -#define mm_stat_v_dtb_miss 4 -#define mm_stat_v_bad_va 5 -#define mm_stat_s_ra 5 -#define mm_stat_v_ra 6 -#define mm_stat_s_opcode 6 -#define mm_stat_v_opcode 11 -#define mvptbr_s_vptb 31 -#define mvptbr_v_vptb 33 -#define va_form_s_va 30 -#define va_form_v_va 3 -#define va_form_s_vptb 31 -#define va_form_v_vptb 33 -#define va_form_nt_s_va 19 -#define va_form_nt_v_va 3 -//.endm - -#endif diff --git a/system/alpha/palcode/ev5_impure.h b/system/alpha/palcode/ev5_impure.h deleted file mode 100644 index ffa910ce2..000000000 --- a/system/alpha/palcode/ev5_impure.h +++ /dev/null @@ -1,423 +0,0 @@ -#ifndef EV5_IMPURE_INCLUDED -#define EV5_IMPURE_INCLUDED - -/* -// This uses the Hudson file format from "impure.h" but with the fields from -// the distrubuted palcode "ev5_impure.sdl" .. pboyle Nov/95 - -//orig file: impure.sdl -//orig -//orig Abstract: PAL impure scratch area and logout area data structure definitions for -//orig Alpha firmware. -//orig -//orig -//orig module $pal_impure; -//orig -//orig Edit Date Who Description -//orig ---- --------- --- --------------------- -//orig 1 7-Jul-93 JEM Initial Entry -//orig 2 18-nov-93 JEM Add shadow bc_ctl and pmctr_ctl to impure area -//orig Delete mvptbr -//orig Calculate pal$logout from end of impure area -//orig 3 6-dec-93 JEM Add pmctr_ctl bitfield definitions -//orig 4 3-feb-94 JEM Remove f31,r31 from impure area; Remove bc_ctl, pmctr_ctl; -//orig add ic_perr_stat, pmctr, dc_perr_stat, sc_stat, sc_addr, sc_ctl, -//orig bc_tag_addr, ei_stat, ei_addr, fill_syn, ld_lock -//orig 5 19-feb-94 JEM add gpr constants, and add f31,r31 back in to be consistent with ev4 -//orig add cns$ipr_offset -//orig 6 18-apr-94 JEM Add shadow bc_ctl and pmctr_ctl to impure area again. -//orig 7 18-jul-94 JEM Add bc_config shadow. Add mchk$sys_base constant to mchk logout frame -//orig -//orig -//orig constant REVISION equals 7 prefix IMPURE$; // Revision number of this file -//orig - -** Macros for saving/restoring data to/from the PAL impure scratch -** area. -** -** The console save state area is larger than the addressibility -** of the HW_LD/ST instructions (10-bit signed byte displacement), -** so some adjustments to the base offsets, as well as the offsets -** within each base region, are necessary. -** -** The console save state area is divided into two segments; the -** CPU-specific segment and the platform-specific segment. The -** state that is saved in the CPU-specific segment includes GPRs, -** FPRs, IPRs, halt code, MCHK flag, etc. All other state is saved -** in the platform-specific segment. -** -** The impure pointer will need to be adjusted by a different offset -** value for each region within a given segment. The SAVE and RESTORE -** macros will auto-magically adjust the offsets accordingly. -** -*/ -#if 0 -#define SAVE_GPR(reg,offset,base) \ - stq_p reg, ((offset-0x200)&0x3FF)(base) - -#define RESTORE_GPR(reg,offset,base) \ - ldq_p reg, ((offset-0x200)&0x3FF)(base) - - -#define SAVE_FPR(reg,offset,base) \ - stt reg, ((offset-0x200)&0x3FF)(base) - -#define RESTORE_FPR(reg,offset,base) \ - ldt reg, ((offset-0x200)&0x3FF)(base) - -#define SAVE_IPR(reg,offset,base) \ - mfpr v0, reg; \ - stq_p v0, ((offset-CNS_Q_IPR)&0x3FF)(base) - -#define RESTORE_IPR(reg,offset,base) \ - ldq_p v0, ((offset-CNS_Q_IPR)&0x3FF)(base); \ - mtpr v0, reg - -#define SAVE_SHADOW(reg,offset,base) \ - stq_p reg, ((offset-CNS_Q_IPR)&0x3FF)(base) - -#define RESTORE_SHADOW(reg,offset,base)\ - ldq_p reg, ((offset-CNS_Q_IPR)&0x3FF)(base) -#else -//#define SEXT10(X) (((X) & 0x200) ? ((X) | 0xfffffffffffffc00) : (X)) -#define SEXT10(X) ((X) & 0x3ff) -//#define SEXT10(X) (((X) << 55) >> 55) - -#define SAVE_GPR(reg,offset,base) \ - stq_p reg, (SEXT10(offset-0x200))(base) - -#define RESTORE_GPR(reg,offset,base) \ - ldq_p reg, (SEXT10(offset-0x200))(base) - - -#define SAVE_FPR(reg,offset,base) \ - stt reg, (SEXT10(offset-0x200))(base) - -#define RESTORE_FPR(reg,offset,base) \ - ldt reg, (SEXT10(offset-0x200))(base) - -#define SAVE_IPR(reg,offset,base) \ - mfpr v0, reg; \ - stq_p v0, (SEXT10(offset-CNS_Q_IPR))(base) - -#define RESTORE_IPR(reg,offset,base) \ - ldq_p v0, (SEXT10(offset-CNS_Q_IPR))(base); \ - mtpr v0, reg - -#define SAVE_SHADOW(reg,offset,base) \ - stq_p reg, (SEXT10(offset-CNS_Q_IPR))(base) - -#define RESTORE_SHADOW(reg,offset,base)\ - ldq_p reg, (SEXT10(offset-CNS_Q_IPR))(base) -#endif -/* orig Structure of the processor-specific impure area */ - -/* orig aggregate impure struct prefix "" tag ""; - * orig cns$flag quadword; - * orig cns$hlt quadword; -*/ - -/* Define base for debug monitor compatibility */ -#define CNS_Q_BASE 0x000 -#define CNS_Q_FLAG 0x100 -#define CNS_Q_HALT 0x108 - - -/* orig constant ( - * orig cns$r0,cns$r1,cns$r2,cns$r3,cns$r4,cns$r5,cns$r6,cns$r7, - * orig cns$r8,cns$r9,cns$r10,cns$r11,cns$r12,cns$r13,cns$r14,cns$r15, - * orig cns$r16,cns$r17,cns$r18,cns$r19,cns$r20,cns$r21,cns$r22,cns$r23, - * orig cns$r24,cns$r25,cns$r26,cns$r27,cns$r28,cns$r29,cns$r30,cns$r31 - * orig ) equals . increment 8 prefix "" tag ""; - * orig cns$gpr quadword dimension 32; -*/ -/* Offset to base of saved GPR area - 32 quadword */ -#define CNS_Q_GPR 0x110 -#define cns_gpr CNS_Q_GPR - -/* orig constant ( - * orig cns$f0,cns$f1,cns$f2,cns$f3,cns$f4,cns$f5,cns$f6,cns$f7, - * orig cns$f8,cns$f9,cns$f10,cns$f11,cns$f12,cns$f13,cns$f14,cns$f15, - * orig cns$f16,cns$f17,cns$f18,cns$f19,cns$f20,cns$f21,cns$f22,cns$f23, - * orig cns$f24,cns$f25,cns$f26,cns$f27,cns$f28,cns$f29,cns$f30,cns$f31 - * orig ) equals . increment 8 prefix "" tag ""; - * orig cns$fpr quadword dimension 32; -*/ -/* Offset to base of saved FPR area - 32 quadwords */ -#define CNS_Q_FPR 0x210 - -/* orig #t=.; - * orig cns$mchkflag quadword; -*/ -#define CNS_Q_MCHK 0x310 - -/* orig constant cns$pt_offset equals .; - * orig constant ( - * orig cns$pt0,cns$pt1,cns$pt2,cns$pt3,cns$pt4,cns$pt5,cns$pt6, - * orig cns$pt7,cns$pt8,cns$pt9,cns$pt10,cns$pt11,cns$pt12,cns$pt13, - * orig cns$pt14,cns$pt15,cns$pt16,cns$pt17,cns$pt18,cns$pt19,cns$pt20, - * orig cns$pt21,cns$pt22,cns$pt23 - * orig ) equals . increment 8 prefix "" tag ""; - * orig cns$pt quadword dimension 24; -*/ -/* Offset to base of saved PALtemp area - 25 quadwords */ -#define CNS_Q_PT 0x318 - -/* orig cns$shadow8 quadword; - * orig cns$shadow9 quadword; - * orig cns$shadow10 quadword; - * orig cns$shadow11 quadword; - * orig cns$shadow12 quadword; - * orig cns$shadow13 quadword; - * orig cns$shadow14 quadword; - * orig cns$shadow25 quadword; -*/ -/* Offset to base of saved PALshadow area - 8 quadwords */ -#define CNS_Q_SHADOW 0x3D8 - -/* Offset to base of saved IPR area */ -#define CNS_Q_IPR 0x418 - -/* orig constant cns$ipr_offset equals .; */ -/* orig cns$exc_addr quadword; */ -#define CNS_Q_EXC_ADDR 0x418 -/* orig cns$pal_base quadword; */ -#define CNS_Q_PAL_BASE 0x420 -/* orig cns$mm_stat quadword; */ -#define CNS_Q_MM_STAT 0x428 -/* orig cns$va quadword; */ -#define CNS_Q_VA 0x430 -/* orig cns$icsr quadword; */ -#define CNS_Q_ICSR 0x438 -/* orig cns$ipl quadword; */ -#define CNS_Q_IPL 0x440 -/* orig cns$ps quadword; // Ibox current mode */ -#define CNS_Q_IPS 0x448 -/* orig cns$itb_asn quadword; */ -#define CNS_Q_ITB_ASN 0x450 -/* orig cns$aster quadword; */ -#define CNS_Q_ASTER 0x458 -/* orig cns$astrr quadword; */ -#define CNS_Q_ASTRR 0x460 -/* orig cns$isr quadword; */ -#define CNS_Q_ISR 0x468 -/* orig cns$ivptbr quadword; */ -#define CNS_Q_IVPTBR 0x470 -/* orig cns$mcsr quadword; */ -#define CNS_Q_MCSR 0x478 -/* orig cns$dc_mode quadword; */ -#define CNS_Q_DC_MODE 0x480 -/* orig cns$maf_mode quadword; */ -#define CNS_Q_MAF_MODE 0x488 -/* orig cns$sirr quadword; */ -#define CNS_Q_SIRR 0x490 -/* orig cns$fpcsr quadword; */ -#define CNS_Q_FPCSR 0x498 -/* orig cns$icperr_stat quadword; */ -#define CNS_Q_ICPERR_STAT 0x4A0 -/* orig cns$pmctr quadword; */ -#define CNS_Q_PM_CTR 0x4A8 -/* orig cns$exc_sum quadword; */ -#define CNS_Q_EXC_SUM 0x4B0 -/* orig cns$exc_mask quadword; */ -#define CNS_Q_EXC_MASK 0x4B8 -/* orig cns$intid quadword; */ -#define CNS_Q_INT_ID 0x4C0 -/* orig cns$dcperr_stat quadword; */ -#define CNS_Q_DCPERR_STAT 0x4C8 -/* orig cns$sc_stat quadword; */ -#define CNS_Q_SC_STAT 0x4D0 -/* orig cns$sc_addr quadword; */ -#define CNS_Q_SC_ADDR 0x4D8 -/* orig cns$sc_ctl quadword; */ -#define CNS_Q_SC_CTL 0x4E0 -/* orig cns$bc_tag_addr quadword; */ -#define CNS_Q_BC_TAG_ADDR 0x4E8 -/* orig cns$ei_stat quadword; */ -#define CNS_Q_EI_STAT 0x4F0 -/* orig cns$ei_addr quadword; */ -#define CNS_Q_EI_ADDR 0x4F8 -/* orig cns$fill_syn quadword; */ -#define CNS_Q_FILL_SYN 0x500 -/* orig cns$ld_lock quadword; */ -#define CNS_Q_LD_LOCK 0x508 -/* orig cns$bc_ctl quadword; // shadow of on chip bc_ctl */ -#define CNS_Q_BC_CTL 0x510 -/* orig cns$pmctr_ctl quadword; // saved frequency select info for performance monitor counter */ -#define CNS_Q_PM_CTL 0x518 -/* orig cns$bc_config quadword; // shadow of on chip bc_config */ -#define CNS_Q_BC_CFG 0x520 - -/* orig constant cns$size equals .; - * orig - * orig constant pal$impure_common_size equals (%x0200 +7) & %xfff8; - * orig constant pal$impure_specific_size equals (.+7) & %xfff8; - * orig constant cns$mchksize equals (.+7-#t) & %xfff8; - * orig constant pal$logout_area equals pal$impure_specific_size ; - * orig end impure; -*/ - -/* This next set of stuff came from the old code ..pb */ -#define CNS_Q_SROM_REV 0x528 -#define CNS_Q_PROC_ID 0x530 -#define CNS_Q_MEM_SIZE 0x538 -#define CNS_Q_CYCLE_CNT 0x540 -#define CNS_Q_SIGNATURE 0x548 -#define CNS_Q_PROC_MASK 0x550 -#define CNS_Q_SYSCTX 0x558 - - - -#define MACHINE_CHECK_CRD_BASE 0 -#define MACHINE_CHECK_SIZE ((CNS_Q_SYSCTX + 7 - CNS_Q_MCHK) & 0xfff8) - - - -/* orig - * orig aggregate EV5PMCTRCTL_BITS structure fill prefix PMCTR_CTL$; - * orig SPROCESS bitfield length 1 ; - * orig FILL_0 bitfield length 3 fill tag $$; - * orig FRQ2 bitfield length 2 ; - * orig FRQ1 bitfield length 2 ; - * orig FRQ0 bitfield length 2 ; - * orig CTL2 bitfield length 2 ; - * orig CTL1 bitfield length 2 ; - * orig CTL0 bitfield length 2 ; - * orig FILL_1 bitfield length 16 fill tag $$; - * orig FILL_2 bitfield length 32 fill tag $$; - * orig end EV5PMCTRCTL_BITS; - * orig - * orig end_module $pal_impure; - * orig - * orig module $pal_logout; - * orig - * orig // - * orig // Start definition of Corrected Error Frame - * orig // - */ - -/* - * orig aggregate crd_logout struct prefix "" tag ""; - */ - -#ifdef SIMOS -#define pal_logout_area 0x600 -#define mchk_crd_base 0 -#endif - -/* orig mchk$crd_flag quadword; */ -#define mchk_crd_flag 0 -/* orig mchk$crd_offsets quadword; */ -#define mchk_crd_offsets 8 -/* orig - * orig // Pal-specific information */ -#define mchk_crd_mchk_code 0x10 -/* orig mchk$crd_mchk_code quadword; - * orig - * orig // CPU-specific information - * orig constant mchk$crd_cpu_base equals . ; - * orig mchk$crd_ei_addr quadword; */ -#define mchk_crd_ei_addr 0x18 -/* orig mchk$crd_fill_syn quadword; */ -#define mchk_crd_fill_syn 0x20 -/* orig mchk$crd_ei_stat quadword; */ -#define mchk_crd_ei_stat 0x28 -/* orig mchk$crd_isr quadword; */ -#define mchk_crd_isr 0x30 - -/* - * Hacked up constants for the turbolaser build. Hope - * this is moreless correct - */ - -#define mchk_crd_whami 0x38 -#define mchk_crd_tldev 0x40 -#define mchk_crd_tlber 0x48 -#define mchk_crd_tlesr0 0x50 -#define mchk_crd_tlesr1 0x58 -#define mchk_crd_tlesr2 0x60 -#define mchk_crd_tlesr3 0x68 -#define mchk_crd_rsvd 0x70 - - -#ifdef SIMOS -/* - * mchk area seems different for tlaser - */ - -#define mchk_crd_size 0x80 -#define mchk_mchk_base (mchk_crd_size) - -#define mchk_tlber 0x0 -#define mchk_tlepaerr 0x8 -#define mchk_tlepderr 0x10 -#define mchk_tlepmerr 0x18 - - -#endif - - -/* orig - * orig // System-specific information - * orig constant mchk$crd_sys_base equals . ; - * orig constant mchk$crd_size equals (.+7) & %xfff8; - * orig - * orig end crd_logout; - * orig // - * orig // Start definition of Machine check logout Frame - * orig // - * orig aggregate logout struct prefix "" tag ""; - * orig mchk$flag quadword; */ -/* orig mchk$offsets quadword; */ -/* orig - * orig // Pal-specific information - * orig mchk$mchk_code quadword; */ -/* - - * orig mchk$pt quadword dimension 24; - * orig - * orig // CPU-specific information - * orig constant mchk$cpu_base equals . ; - * orig mchk$exc_addr quadword; - * orig mchk$exc_sum quadword; - * orig mchk$exc_mask quadword; - * orig mchk$pal_base quadword; - * orig mchk$isr quadword; - * orig mchk$icsr quadword; - * orig mchk$ic_perr_stat quadword; - * orig mchk$dc_perr_stat quadword; - * orig mchk$va quadword; - * orig mchk$mm_stat quadword; - * orig mchk$sc_addr quadword; - * orig mchk$sc_stat quadword; - * orig mchk$bc_tag_addr quadword; - * orig mchk$ei_addr quadword; - * orig mchk$fill_syn quadword; - * orig mchk$ei_stat quadword; - * orig mchk$ld_lock quadword; - * orig - * orig // System-specific information - * orig - * orig constant mchk$sys_base equals . ; - * orig mchk$sys_ipr1 quadword ; // Holder for system-specific stuff - * orig - * orig constant mchk$size equals (.+7) & %xfff8; - * orig - * orig - * orig constant mchk$crd_base equals 0 ; - * orig constant mchk$mchk_base equals mchk$crd_size ; - * orig - * orig - * orig end logout; - * orig - * orig end_module $pal_logout; -*/ - - - - -/* this is lingering in the old ladbx code but looks like it was from ev4 days. - * This was 0x160 in the old days..pb -*/ -#define LAF_K_SIZE MACHINE_CHECK_SIZE -#endif diff --git a/system/alpha/palcode/ev5_osfalpha_defs.h b/system/alpha/palcode/ev5_osfalpha_defs.h deleted file mode 100644 index 08a110075..000000000 --- a/system/alpha/palcode/ev5_osfalpha_defs.h +++ /dev/null @@ -1,160 +0,0 @@ -#ifndef EV5_OSFALPHA_DEFS_INCLUDED -#define EV5_OSFALPHA_DEFS_INCLUDED 1 - - -// from ev5_osfalpha_defs.mar from Lance's fetch directory -// lowercaseified and $ changed to _ and reformatting for gas...pb Nov/95 - -//orig .MACRO $OSF_ALPHADEFS -//orig OSF_ALPHADEF_VER == 5 ; Flag the version number of this file. -//orig .ENDM -//orig .MACRO $OSF_PSDEF,$GBL -//orig $DEFINI OSFPS,$GBL -//orig;+ -//orig; PS Layout - PS -//orig; Loc Size name function -//orig; ------ ------ ----- ----------------------------------- -//orig; <0:2> 3 IPL Prio level -//orig; <3> 1 CM Current Mode -//orig;- - -#define osfps_v_mode 3 -#define osfps_m_mode (1< 32 PFN Page Frame Number -//orig; <31:16> 16 SOFT Bits reserved for software use -//orig; <15:14> 2 -//orig; <13> 1 UWE User write enable -//orig; <12> 1 KWE Kernel write enable -//orig; <11:10> 2 -//orig; <9> 1 URE User read enable -//orig; <8> 1 KRE Kernel read enable -//orig; <7:6> 2 RES Reserved SBZ -//orig; <5> 1 HPF Huge Page Flag -//orig; <4> 1 ASM Wild card address space number match -//orig; <3> 1 FOE Fault On execute -//orig; <2> 1 FOW Fault On Write -//orig; <1> 1 FOR Fault On Read -//orig; <0> 1 V valid bit -//orig;- - -//orig .MACRO _OSF_PTEDEF,_GBL -//orig _DEFINI OSFPTE,_GBL - -#define osfpte_v_pfn 32 -#define osfpte_m_soft (0xFFFF0000) -#define osfpte_v_soft 16 -#define osfpte_m_uwe (0x2000) -#define osfpte_v_uwe 13 -#define osfpte_m_kwe (0x1000) -#define osfpte_v_kwe 12 -#define osfpte_m_ure (0x0200) -#define osfpte_v_ure 9 -#define osfpte_m_kre (0x0100) -#define osfpte_v_kre 8 -#define osfpte_m_hpf (0x0020) -#define osfpte_v_hpf 5 -#define osfpte_m_asm (0x0010) -#define osfpte_v_asm 4 -#define osfpte_m_foe (0x0008) -#define osfpte_v_foe 3 -#define osfpte_m_fow (0x0004) -#define osfpte_v_fow 2 -#define osfpte_m_for (0x0002) -#define osfpte_v_for 1 -#define osfpte_m_v (0x0001) -#define osfpte_v_v 0 - -#define osfpte_m_ksegbits (osfpte_m_kre | osfpte_m_kwe | osfpte_m_v | osfpte_m_asm) -#define osfpte_m_prot (osfpte_m_ure+osfpte_m_uwe | osfpte_m_kre | osfpte_m_kwe) - -//orig _DEFEND OSFPTE,_GBL,DEF -//orig .ENDM - -//orig;+ -//orig; VA layout - symbol prefix VA_ -//orig; -//orig; Loc Size name function -//orig; ------ ------ ------- ----------------------------------- -//orig; <42:33> 10 SEG1 First seg table offset for mapping -//orig; <32:23> 10 SEG2 Second seg table offset for mapping -//orig; <22:13> 10 SEG3 Third seg table offset for mapping -//orig; <12:0> 13 OFFSET Byte within page -//orig;- -//orig .MACRO _OSF_VADEF,_GBL -//orig _DEFINI OSFVA,_GBL - -#define osfva_m_offset (0x000000001FFF) -#define osfva_v_offset 0 -#define osfva_m_seg3 (0x0000007FE000) -#define osfva_v_seg3 13 -#define osfva_m_seg2 (0x0001FF800000) -#define osfva_v_seg2 23 -#define osfva_m_seg1 (0x7FE00000000) -#define osfva_v_seg1 33 - -//orig _DEFEND OSFVA,_GBL,DEF -//orig .ENDM -//orig;+ -//orig; PRIVILEGED CONTEXT BLOCK (PCB) -//orig;- -//orig .MACRO _OSF_PCBDEF,_GBL -//orig _DEFINI OSFPCB,_GBL - -#define osfpcb_q_ksp (0x0000) -#define osfpcb_q_usp (0x0008) -#define osfpcb_q_Usp (0x0008) -#define osfpcb_q_mmptr (0x0010) -#define osfpcb_q_Mmptr (0x0010) -#define osfpcb_l_cc (0x0018) -#define osfpcb_l_asn (0x001C) -#define osfpcb_q_unique (0x0020) -#define osfpcb_q_fen (0x0028) -#define osfpcb_v_pme 62 - -//orig _DEFEND OSFPCB,_GBL,DEF -//orig .ENDM -//orig;+ -//orig; Stack Frame -//orig;- -//orig .MACRO _OSF_SFDEF,_GBL -//orig _DEFINI OSFSF,_GBL - -#define osfsf_ps (0x00) -#define osfsf_pc (0x08) -#define osfsf_gp (0x10) -#define osfsf_a0 (0x18) -#define osfsf_a1 (0x20) -#define osfsf_a2 (0x28) -#define osfsf_c_size (0x30) - -//orig _DEFEND OSFSF,_GBL,DEF -//orig .ENDM - -#endif diff --git a/system/alpha/palcode/ev5_paldef.h b/system/alpha/palcode/ev5_paldef.h deleted file mode 100644 index 5f9241b12..000000000 --- a/system/alpha/palcode/ev5_paldef.h +++ /dev/null @@ -1,185 +0,0 @@ -#ifndef EV5_PALDEF_INCLUDED -#define EV5_PALDEF_INCLUDED 1 - -// from ev5_paldef.mar from Lance's fetch directory...pb Nov/95 -// some entries have been superceeded by the more recent evt_defs.h - -// These are lower-caseified and have the $ signs (unnecessarily we now discover) removed. - -// Note that at the bottom of this file is the version of ev5_defs.mar -// which is more recent than the top part of the file and contains overlapping information...pb Nov/95 - -// .MACRO PALDEFS -// PALDEF_VER == 1 ; Flag the version number of this file. -// .ENDM -// -// -// .MACRO _HALT_CODES,_GBL -// _DEFINI HALT_CODES,_GBL - -#define hlt_c_reset 0 -#define hlt_c_hw_halt 1 -#define hlt_c_ksp_inval 2 -#define hlt_c_scbb_inval 3 -#define hlt_c_ptbr_inval 4 -#define hlt_c_sw_halt 5 -#define hlt_c_dbl_mchk 6 -#define hlt_c_mchk_from_pal 7 -#define hlt_c_start 32 -#define hlt_c_callback 33 -#define hlt_c_mpstart 34 -#define hlt_c_lfu_start 35 - -// halt codes above 255 reserved for platform specific errors -// _DEFEND HALT_CODES,_GBL,DEF -// .ENDM -// .MACRO _MCHK_CODES,_GBL -// _DEFINI MCHK_CODES,_GBL - -#define mchk_c_tperr (64<<1) -#define mchk_c_tcperr (65<<1) -#define mchk_c_herr (66<<1) -#define mchk_c_ecc_c (67<<1) -#define mchk_c_ecc_nc (68<<1) -#define mchk_c_unknown (69<<1) -#define mchk_c_cacksoft (70<<1) -#define mchk_c_bugcheck (71<<1) -#define mchk_c_os_bugcheck (72<<1) -#define mchk_c_dcperr (73<<1) -#define mchk_c_icperr (74<<1) -#define mchk_c_retryable_ird (75<<1) -#define mchk_c_proc_hrd_error (76<<1) -#define mchk_c_scperr (77<<1) -#define mchk_c_bcperr (78<<1) -//; mchk codes above 255 reserved for platform specific errors - - -#define mchk_c_read_nxm (256<<1) -#define mchk_c_sys_hrd_error (257<<1) -#define mchk_c_sys_ecc (258<<1) - -// _DEFEND MCHK_CODES,_GBL,DEF -// .ENDM - -// .MACRO _EV5_MM,_GBL -// _DEFINI _EV5_MM,_GBL - -#define page_seg_size_bits 10 -#define page_offset_size_bits 13 -#define page_size_bytes 8192 -#define va_size_bits 43 -#define pa_size_bits 45 - -// _DEFEND _EV5_MM,_GBL,DEF -// .ENDM - -// .MACRO _PALTEMP,_GBL -// _DEFINI _PALTEMP,_GBL - -// replaced by ev5_defs.h #define pt0 (0x140) -// replaced by ev5_defs.h #define pt1 (0x141) -// replaced by ev5_defs.h #define pt2 (0x142) -#define pt_entuna (0x142) -// replaced by ev5_defs.h #define pt3 (0x143) -#define pt_impure (0x143) -// replaced by ev5_defs.h #define pt4 (0x144) -// replaced by ev5_defs.h #define pt5 (0x145) -// replaced by ev5_defs.h #define pt6 (0x146) -// replaced by ev5_defs.h #define pt7 (0x147) -#define pt_entif (0x147) -// replaced by ev5_defs.h #define pt8 (0x148) -#define pt_intmask (0x148) -// replaced by ev5_defs.h #define pt9 (0x149) -#define pt_entsys (0x149) -#define pt_ps (0x149) -// replaced by ev5_defs.h #define pt10 (0x14a) -// replaced by ev5_defs.h #define pt11 (0x14b) -#define pt_trap (0x14b) -#define pt_entint (0x14b) -// replaced by ev5_defs.h #define pt12 (0x14c) -#define pt_entarith (0x14c) -// replaced by ev5_defs.h #define pt13 (0x14d) -#define pt_sys0 (0x14d) -// replaced by ev5_defs.h #define pt14 (0x14e) -#define pt_sys1 (0x14e) -// replaced by ev5_defs.h #define pt15 (0x14f) -#define pt_sys2 (0x14f) -// replaced by ev5_defs.h #define pt16 (0x150) -#define pt_whami (0x150) -#define pt_mces (0x150) -#define pt_misc (0x150) -// replaced by ev5_defs.h #define pt17 (0x151) -#define pt_scc (0x151) -#define pt_sysval (0x151) -// replaced by ev5_defs.h #define pt18 (0x152) -#define pt_prbr (0x152) -#define pt_usp (0x152) -// replaced by ev5_defs.h #define pt19 (0x153) -#define pt_ksp (0x153) -// replaced by ev5_defs.h #define pt20 (0x154) -#define pt_ptbr (0x154) -// replaced by ev5_defs.h #define pt21 (0x155) -#define pt_vptbr (0x155) -#define pt_entmm (0x155) -// replaced by ev5_defs.h #define pt22 (0x156) -#define pt_scbb (0x156) -#define pt_kgp (0x156) -// replaced by ev5_defs.h #define pt23 (0x157) -#define pt_pcbb (0x157) - - -#define pt_misc_v_switch 48 -#define pt_misc_v_cm 56 - -// _DEFEND _PALTEMP,_GBL,DEF -// .ENDM - -// .MACRO _OSF_MMCSR_DEF,_GBL -// _DEFINI OSFMMCSR,_GBL - -#define mmcsr_c_tnv 0 -#define mmcsr_c_acv 1 -#define mmcsr_c_for 2 -#define mmcsr_c_foe 3 -#define mmcsr_c_fow 4 - -// _DEFEND OSFMMCSR,_GBL,DEF -// .ENDM - -// .MACRO _MM_STAT_DEF,_GBL -// _DEFINI MMSTATDEF,_GBL - -#define mm_stat_m_opcode (0x3F) -#define mm_stat_m_ra (0x1F) -#define evx_opc_sync (0x18) -#define EVX_OPC_SYNC (0x18) -#define evx_opc_hw_ld (0x1B) - -// _DEFEND MMSTATDEF,_GBL,DEF -// .ENDM - -// .MACRO _OSF_A0_DEF,_GBL -// _DEFINI OSFA0DEF,_GBL - -#define osf_a0_bpt (0x0) -#define osf_a0_bugchk (0x1) -#define osf_a0_gentrap (0x2) -#define osf_a0_fen (0x3) -#define osf_a0_opdec (0x4) - -// _DEFEND OSFA0DEF,_GBL,DEF -// .ENDM - -// .MACRO _EV5_IPLDEF,_GBL -// _DEFINI EV5_IPLDEF,_GBL - -#define ipl_machine_check 31 -#define ipl_powerfail 30 -#define ipl_perf_count 29 -#define ipl_clock 22 -#define ipl_interprocessor 22 - -// _DEFEND EV5_IPLDEF,_GBL,DEF -// .ENDM - -#endif diff --git a/system/alpha/palcode/fromHudsonMacros.h b/system/alpha/palcode/fromHudsonMacros.h deleted file mode 100644 index 4b22d87ac..000000000 --- a/system/alpha/palcode/fromHudsonMacros.h +++ /dev/null @@ -1,145 +0,0 @@ -#ifndef HUDSON_MACROS_LOADED -#define HUDSON_MACROS_LOADED 1 - -/* - * VID: [T1.2] PT: [Fri Apr 21 16:47:16 1995] SF: [macros.h] - * TI: [/sae_users/cruz/bin/vice -iplatform.s -l// -p# -DEB164 -h -m -aeb164 ] - */ -/* -***************************************************************************** -** * -** Copyright © 1993, 1994 * -** by Digital Equipment Corporation, Maynard, Massachusetts. * -** * -** All Rights Reserved * -** * -** Permission is hereby granted to use, copy, modify and distribute * -** this software and its documentation, in both source code and * -** object code form, and without fee, for the purpose of distribution * -** of this software or modifications of this software within products * -** incorporating an integrated circuit implementing Digital's AXP * -** architecture, regardless of the source of such integrated circuit, * -** provided that the above copyright notice and this permission notice * -** appear in all copies, and that the name of Digital Equipment * -** Corporation not be used in advertising or publicity pertaining to * -** distribution of the document or software without specific, written * -** prior permission. * -** * -** Digital Equipment Corporation disclaims all warranties and/or * -** guarantees with regard to this software, including all implied * -** warranties of fitness for a particular purpose and merchantability, * -** and makes no representations regarding the use of, or the results * -** of the use of, the software and documentation in terms of correctness, * -** accuracy, reliability, currentness or otherwise; and you rely on * -** the software, documentation and results solely at your own risk. * -** * -** AXP is a trademark of Digital Equipment Corporation. * -** * -***************************************************************************** -** -** FACILITY: -** -** DECchip 21164 PALcode -** -** MODULE: -** -** macros.h -** -** MODULE DESCRIPTION: -** -** DECchip 21164 PALcode macro definitions -** -** AUTHOR: ER -** -** CREATION DATE: 29-Nov-1993 -** -** $Id: fromHudsonMacros.h,v 1.1.1.1 1997/10/30 23:27:19 verghese Exp $ -** -** MODIFICATION HISTORY: -** -** $Log: fromHudsonMacros.h,v $ -** Revision 1.1.1.1 1997/10/30 23:27:19 verghese -** current 10/29/97 -** -** Revision 1.1 1995/11/18 01:46:23 boyle -** Initial revision -** -** Revision 1.5 1994/07/08 17:03:12 samberg -** Changes to support platform specific additions -** -** Revision 1.4 1994/05/20 19:24:19 ericr -** Moved STALL macro from osfpal.s to here -** Added LDLI macro -** -** Revision 1.3 1994/05/20 18:08:14 ericr -** Changed line comments to C++ style comment character -** -** Revision 1.2 1994/02/28 18:45:51 ericr -** Fixed EGORE related bugs -** -** Revision 1.1 1993/12/16 21:55:05 eric -** Initial revision -** -** -**-- -*/ - -#define STALL \ - mfpr r31, pt0 - -#define NOP \ - bis $31, $31, $31 - -/* -** Align code on an 8K byte page boundary. -*/ - -#define ALIGN_PAGE \ - .align 13 - -/* -** Align code on a 32 byte block boundary. -*/ - -#define ALIGN_BLOCK \ - .align 5 - -/* -** Align code on a quadword boundary. -*/ - -#define ALIGN_BRANCH \ - .align 3 - -/* -** Hardware vectors go in .text 0 sub-segment. -*/ - -#define HDW_VECTOR(offset) \ - . = offset - -/* -** Privileged CALL_PAL functions are in .text 1 sub-segment. -*/ - -#define CALL_PAL_PRIV(vector) \ - . = (PAL_CALL_PAL_PRIV_ENTRY+(vector<<6)) - -/* -** Unprivileged CALL_PAL functions are in .text 1 sub-segment, -** the privileged bit is removed from these vectors. -*/ - -#define CALL_PAL_UNPRIV(vector) \ - . = (PAL_CALL_PAL_UNPRIV_ENTRY+((vector&0x3F)<<6)) - -/* -** Implements a load "immediate" longword function -*/ -#define LDLI(reg,val) \ - ldah reg, ((val+0x8000) >> 16)(zero); \ - lda reg, (val&0xffff)(reg) - - - -#endif diff --git a/system/alpha/palcode/fromHudsonOsf.h b/system/alpha/palcode/fromHudsonOsf.h deleted file mode 100644 index f9cb2f747..000000000 --- a/system/alpha/palcode/fromHudsonOsf.h +++ /dev/null @@ -1,554 +0,0 @@ -#ifndef FROMHUDSONOSF_INCLUDED -#define FROMHUDSONOSF_INCLUDED 1 -/* - * VID: [T1.2] PT: [Fri Apr 21 16:47:14 1995] SF: [osf.h] - * TI: [/sae_users/cruz/bin/vice -iplatform.s -l// -p# -DEB164 -h -m -aeb164 ] - */ -#define __OSF_LOADED 1 -/* -***************************************************************************** -** * -** Copyright © 1993, 1994 * -** by Digital Equipment Corporation, Maynard, Massachusetts. * -** * -** All Rights Reserved * -** * -** Permission is hereby granted to use, copy, modify and distribute * -** this software and its documentation, in both source code and * -** object code form, and without fee, for the purpose of distribution * -** of this software or modifications of this software within products * -** incorporating an integrated circuit implementing Digital's AXP * -** architecture, regardless of the source of such integrated circuit, * -** provided that the above copyright notice and this permission notice * -** appear in all copies, and that the name of Digital Equipment * -** Corporation not be used in advertising or publicity pertaining to * -** distribution of the document or software without specific, written * -** prior permission. * -** * -** Digital Equipment Corporation disclaims all warranties and/or * -** guarantees with regard to this software, including all implied * -** warranties of fitness for a particular purpose and merchantability, * -** and makes no representations regarding the use of, or the results * -** of the use of, the software and documentation in terms of correctness, * -** accuracy, reliability, currentness or otherwise; and you rely on * -** the software, documentation and results solely at your own risk. * -** * -** AXP is a trademark of Digital Equipment Corporation. * -** * -***************************************************************************** -** -** FACILITY: -** -** DECchip 21164 PALcode -** -** MODULE: -** -** osf.h -** -** MODULE DESCRIPTION: -** -** OSF/1 specific definitions -** -** AUTHOR: ER -** -** CREATION DATE: 24-Nov-1993 -** -** $Id: fromHudsonOsf.h,v 1.1.1.1 1997/10/30 23:27:19 verghese Exp $ -** -** MODIFICATION HISTORY: -** -** $Log: fromHudsonOsf.h,v $ -** Revision 1.1.1.1 1997/10/30 23:27:19 verghese -** current 10/29/97 -** -** Revision 1.1 1995/11/18 01:46:31 boyle -** Initial revision -** -** Revision 1.11 1995/04/21 02:06:30 fdh -** Replaced C++ style comments with Standard C style comments. -** -** Revision 1.10 1994/09/26 14:17:47 samberg -** Complete VICE work and EB164/SD164 breakout. -** -** Revision 1.9 1994/07/26 17:39:10 samberg -** Changes for SD164. -** -** Revision 1.8 1994/07/08 17:03:48 samberg -** Changes to support platform specific additions -** -** Revision 1.7 1994/05/20 19:23:51 ericr -** Moved STACK_FRAME macro from osfpal.s to here -** -** Revision 1.6 1994/05/20 18:08:19 ericr -** Changed line comments to C++ style comment character -** -** Revision 1.5 1994/01/11 18:43:33 ericr -** Removed PAL version/revision and size constants -** -** Revision 1.4 1994/01/05 16:22:32 ericr -** Added more SCB vector offsets and MCHK error code -** -** Revision 1.3 1994/01/03 19:35:40 ericr -** Derive mask definitions from field constants -** -** Revision 1.2 1993/12/22 20:43:01 eric -** Added mask definitions for MCES bits -** -** Revision 1.1 1993/12/16 21:55:05 eric -** Initial revision -** -** -**-- -*/ - -/* -** Seg0 and Seg1 Virtual Address (VA) Format -** -** Loc Size Name Function -** ----- ---- ---- --------------------------------- -** <42:33> 10 SEG1 First level page table offset -** <32:23> 10 SEG2 Second level page table offset -** <22:13> 10 SEG3 Third level page table offset -** <12:00> 13 OFFSET Byte within page offset -*/ - -#define VA_V_SEG1 33 -#define VA_M_SEG1 (0x3FF< 32 PFN Page Frame Number -** <31:16> 16 SW Reserved for software -** <15:14> 2 RSV0 Reserved for hardware SBZ -** <13> 1 UWE User Write Enable -** <12> 1 KWE Kernel Write Enable -** <11:10> 2 RSV1 Reserved for hardware SBZ -** <9> 1 URE User Read Enable -** <8> 1 KRE Kernel Read Enable -** <7> 1 RSV2 Reserved for hardware SBZ -** <6:5> 2 GH Granularity Hint -** <4> 1 ASM Address Space Match -** <3> 1 FOE Fault On Execute -** <2> 1 FOW Fault On Write -** <1> 1 FOR Fault On Read -** <0> 1 V Valid -*/ - -#define PTE_V_PFN 32 -#define PTE_M_PFN 0xFFFFFFFF00000000 -#define PTE_V_SW 16 -#define PTE_M_SW 0x00000000FFFF0000 -#define PTE_V_UWE 13 -#define PTE_M_UWE (1< 1 CM Current Mode -** <2:0> 3 IPL Interrupt Priority Level -**/ - -#define PS_V_CM 3 -#define PS_M_CM (1< 1 MIP Machine check in progress -** <1> 1 SCE System correctable error in progress -** <2> 1 PCE Processor correctable error in progress -** <3> 1 DPC Disable PCE error reporting -** <4> 1 DSC Disable SCE error reporting -*/ - -#define MCES_V_MIP 0 -#define MCES_M_MIP (1< 8 ID Who-Am-I identifier -** <15:8> 1 SWAP Swap PALcode flag - character 'S' -*/ - -#define WHAMI_V_SWAP 8 -#define WHAMI_M_SWAP (1<> 16)(zero); \ - lda reg, (val&0xffff)(reg) - diff --git a/system/alpha/palcode/osf.h b/system/alpha/palcode/osf.h deleted file mode 100644 index 316d83cf1..000000000 --- a/system/alpha/palcode/osf.h +++ /dev/null @@ -1,545 +0,0 @@ -/* - * VID: [T1.2] PT: [Fri Apr 21 16:47:14 1995] SF: [osf.h] - * TI: [/sae_users/cruz/bin/vice -iplatform.s -l// -p# -DEB164 -h -m -aeb164 ] - */ -#define __OSF_LOADED 1 -/* -***************************************************************************** -** * -** Copyright © 1993, 1994 * -** by Digital Equipment Corporation, Maynard, Massachusetts. * -** * -** All Rights Reserved * -** * -** Permission is hereby granted to use, copy, modify and distribute * -** this software and its documentation, in both source code and * -** object code form, and without fee, for the purpose of distribution * -** of this software or modifications of this software within products * -** incorporating an integrated circuit implementing Digital's AXP * -** architecture, regardless of the source of such integrated circuit, * -** provided that the above copyright notice and this permission notice * -** appear in all copies, and that the name of Digital Equipment * -** Corporation not be used in advertising or publicity pertaining to * -** distribution of the document or software without specific, written * -** prior permission. * -** * -** Digital Equipment Corporation disclaims all warranties and/or * -** guarantees with regard to this software, including all implied * -** warranties of fitness for a particular purpose and merchantability, * -** and makes no representations regarding the use of, or the results * -** of the use of, the software and documentation in terms of correctness, * -** accuracy, reliability, currentness or otherwise; and you rely on * -** the software, documentation and results solely at your own risk. * -** * -** AXP is a trademark of Digital Equipment Corporation. * -** * -***************************************************************************** -** -** FACILITY: -** -** DECchip 21164 PALcode -** -** MODULE: -** -** osf.h -** -** MODULE DESCRIPTION: -** -** OSF/1 specific definitions -** -** AUTHOR: ER -** -** CREATION DATE: 24-Nov-1993 -** -** $Id: osf.h,v 1.1.1.1 1997/10/30 23:27:19 verghese Exp $ -** -** MODIFICATION HISTORY: -** -** $Log: osf.h,v $ -** Revision 1.1.1.1 1997/10/30 23:27:19 verghese -** current 10/29/97 -** -** Revision 1.11 1995/04/21 02:06:30 fdh -** Replaced C++ style comments with Standard C style comments. -** -** Revision 1.10 1994/09/26 14:17:47 samberg -** Complete VICE work and EB164/SD164 breakout. -** -** Revision 1.9 1994/07/26 17:39:10 samberg -** Changes for SD164. -** -** Revision 1.8 1994/07/08 17:03:48 samberg -** Changes to support platform specific additions -** -** Revision 1.7 1994/05/20 19:23:51 ericr -** Moved STACK_FRAME macro from osfpal.s to here -** -** Revision 1.6 1994/05/20 18:08:19 ericr -** Changed line comments to C++ style comment character -** -** Revision 1.5 1994/01/11 18:43:33 ericr -** Removed PAL version/revision and size constants -** -** Revision 1.4 1994/01/05 16:22:32 ericr -** Added more SCB vector offsets and MCHK error code -** -** Revision 1.3 1994/01/03 19:35:40 ericr -** Derive mask definitions from field constants -** -** Revision 1.2 1993/12/22 20:43:01 eric -** Added mask definitions for MCES bits -** -** Revision 1.1 1993/12/16 21:55:05 eric -** Initial revision -** -** -**-- -*/ - -/* -** Seg0 and Seg1 Virtual Address (VA) Format -** -** Loc Size Name Function -** ----- ---- ---- --------------------------------- -** <42:33> 10 SEG1 First level page table offset -** <32:23> 10 SEG2 Second level page table offset -** <22:13> 10 SEG3 Third level page table offset -** <12:00> 13 OFFSET Byte within page offset -*/ - -#define VA_V_SEG1 33 -#define VA_M_SEG1 (0x3FF< 32 PFN Page Frame Number -** <31:16> 16 SW Reserved for software -** <15:14> 2 RSV0 Reserved for hardware SBZ -** <13> 1 UWE User Write Enable -** <12> 1 KWE Kernel Write Enable -** <11:10> 2 RSV1 Reserved for hardware SBZ -** <9> 1 URE User Read Enable -** <8> 1 KRE Kernel Read Enable -** <7> 1 RSV2 Reserved for hardware SBZ -** <6:5> 2 GH Granularity Hint -** <4> 1 ASM Address Space Match -** <3> 1 FOE Fault On Execute -** <2> 1 FOW Fault On Write -** <1> 1 FOR Fault On Read -** <0> 1 V Valid -*/ - -#define PTE_V_PFN 32 -#define PTE_M_PFN 0xFFFFFFFF00000000 -#define PTE_V_SW 16 -#define PTE_M_SW 0x00000000FFFF0000 -#define PTE_V_UWE 13 -#define PTE_M_UWE (1< 1 CM Current Mode -** <2:0> 3 IPL Interrupt Priority Level -**/ - -#define PS_V_CM 3 -#define PS_M_CM (1< 1 MIP Machine check in progress -** <1> 1 SCE System correctable error in progress -** <2> 1 PCE Processor correctable error in progress -** <3> 1 DPC Disable PCE error reporting -** <4> 1 DSC Disable SCE error reporting -*/ - -#define MCES_V_MIP 0 -#define MCES_M_MIP (1< 8 ID Who-Am-I identifier -** <15:8> 1 SWAP Swap PALcode flag - character 'S' -*/ - -#define WHAMI_V_SWAP 8 -#define WHAMI_M_SWAP (1<