From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 30 Jul 2009 05:24:00 +0000 (-0700)
Subject: ARM: Mul and mla ignore the c and v flags, but we were setting them to 1.
X-Git-Tag: Calvin_Submission~194^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4971331b4f8f9e79cf6dcc564a85fb432bef8b9c;p=gem5.git

ARM: Mul and mla ignore the c and v flags, but we were setting them to 1.
---

diff --git a/src/arch/arm/isa/formats/pred.isa b/src/arch/arm/isa/formats/pred.isa
index 50e162f3d..e90788c91 100644
--- a/src/arch/arm/isa/formats/pred.isa
+++ b/src/arch/arm/isa/formats/pred.isa
@@ -105,7 +105,8 @@ let {{
     def getCcCode(flagtype):
         icReg = icImm = iv = ''
         if flagtype == "none":
-            icReg = icImm = iv = '1'
+            icReg = icImm = 'Cpsr<29:>'
+            iv = 'Cpsr<28:>'
         elif flagtype == "add":
             icReg = icImm = 'findCarry(32, resTemp, Rn, op2)'
             iv = 'findOverflow(32, resTemp, Rn, op2)'
@@ -125,7 +126,8 @@ let {{
     def getImmCcCode(flagtype):
         ivValue = icValue = ''
         if flagtype == "none":
-            icValue = ivValue = '1'
+            icValue = 'Cpsr<29:>'
+            ivValue = 'Cpsr<28:>'
         elif flagtype == "add":
             icValue = 'findCarry(32, resTemp, Rn, rotated_imm)'
             ivValue = 'findOverflow(32, resTemp, Rn, rotated_imm)'