From: Marcin Kościelnicki <koriakin@0x04.net>
Date: Tue, 13 Aug 2019 18:05:49 +0000 (+0000)
Subject: minor review fixes
X-Git-Tag: working-ls180~1097^2~15
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=49765ec19ea63bff5f04e28e5729d5852a2f8287;p=yosys.git

minor review fixes
---

diff --git a/CHANGELOG b/CHANGELOG
index 56e5c9017..bd4cd1b1b 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -20,8 +20,10 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Improve attribute and parameter encoding in JSON to avoid ambiguities between
       bit vectors and strings containing [01xz]*
     - Added "clkbufmap" pass
-    - Added "synth_xilinx -ise" for Spartan 6 (experimental)
-    - "synth_xilinx" now automatically inserts clock buffers
+    - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
+    - Added "synth_xilinx -ise" (experimental)
+    - Added "synth_xilinx -iopad"
+    - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
 
 Yosys 0.8 .. Yosys 0.8-dev
 --------------------------
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index e9e8dbfea..4069094a6 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -64,7 +64,7 @@ struct SynthXilinxPass : public ScriptPass
 		log("        (this feature is experimental and incomplete)\n");
 		log("\n");
 		log("    -ise\n");
-		log("        generate an output netlist suitable for ISE\n");
+		log("        generate an output netlist suitable for ISE (enables -iopad)\n");
 		log("\n");
 		log("    -nobram\n");
 		log("        disable inference of block rams\n");