From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 10 May 2023 11:33:26 +0000 (+0100)
Subject: extend previous hard-coded magic constant (256) used to indicate
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4977a9b88acaacfce5367bb079b21111f6026e95;p=openpower-isa.git

extend previous hard-coded magic constant (256) used to indicate
"effectively unlimited" (see check_extsign) out to 1024. it would be
better to set this at the bare-minimum limit (257, 258) as it requests
that python runtime create massive-large ints
---

diff --git a/src/openpower/decoder/helpers.py b/src/openpower/decoder/helpers.py
index 9211e5ab..0bdd4f29 100644
--- a/src/openpower/decoder/helpers.py
+++ b/src/openpower/decoder/helpers.py
@@ -3,6 +3,7 @@ import struct
 import sys
 from openpower.decoder.selectable_int import (SelectableInt, onebit,
                                               selectconcat, FieldSelectableInt)
+from openpower.decoder.selectable_int import EFFECTIVELY_UNLIMITED as EU
 from nmutil.divmod import trunc_divs, trunc_rems
 from operator import floordiv, mod
 from openpower.decoder.selectable_int import selectltu as ltu
@@ -39,19 +40,19 @@ def exts(value, bits):
 
 
 def EXTS(value):
-    """ extends sign bit out from current MSB to all 256 bits
+    """ extends sign bit out from current MSB to MAX limit bits
     """
     log("EXTS", value, type(value))
     assert isinstance(value, SelectableInt)
-    return SelectableInt(exts(value.value, value.bits) & ((1 << 256)-1), 256)
+    return SelectableInt(exts(value.value, value.bits) & ((1 << EU)-1), EU)
 
 
 def EXTZ(value):
-    """ zero extend to 256 bits
+    """ zero extend to EFFECTIVELY_UNLIMITED bits
     """
     if isinstance(value, SelectableInt):
         value = value.value
-    return SelectableInt(value & ((1 << 256) - 1), 256)
+    return SelectableInt(value & ((1 << EU) - 1), EU)
 
 
 def EXTS64(value):
diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index a4c26965..f0c43bc1 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -37,7 +37,8 @@ from openpower.decoder.power_enums import (FPTRANS_INSNS, CRInSel, CROutSel,
 from openpower.decoder.power_insn import SVP64Instruction
 from openpower.decoder.power_svp64 import SVP64RM, decode_extra
 from openpower.decoder.selectable_int import (FieldSelectableInt,
-                                              SelectableInt, selectconcat)
+                                              SelectableInt, selectconcat,
+                                              EFFECTIVELY_UNLIMITED)
 from openpower.fpscr import FPSCRState
 from openpower.util import LogKind, log
 
@@ -1226,7 +1227,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
         self.cr_backup = 0  # sigh, dreadful hack: for fail-first (VLi)
 
         # "undefined", just set to variable-bit-width int (use exts "max")
-        # self.undefined = SelectableInt(0, 256)  # TODO, not hard-code 256!
+        # self.undefined = SelectableInt(0, EFFECTIVELY_UNLIMITED)
 
         self.namespace = {}
         self.namespace.update(self.spr)
@@ -2402,7 +2403,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
         if name == 'CR0':  # ignore, done already (above)
             return
         if isinstance(output, int):
-            output = SelectableInt(output, 256)
+            output = SelectableInt(output, EFFECTIVELY_UNLIMITED)
         # write carry flafs
         if name in ['CA', 'CA32']:
             if carry_en:
@@ -2439,7 +2440,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
         # check zeroing due to predicate bit being zero
         if self.is_svp64_mode and self.pred_dst_zero:
             log('zeroing reg %s %s' % (str(regnum), str(output)), is_vec)
-            output = SelectableInt(0, 256)
+            output = SelectableInt(0, EFFECTIVELY_UNLIMITED)
         log("write reg %s%s 0x%x ew %d" % (reg_prefix, str(regnum),
                                            output.value, ew_dst),
             kind=LogKind.InstrInOuts)
diff --git a/src/openpower/decoder/selectable_int.py b/src/openpower/decoder/selectable_int.py
index ee50e081..ee8ef7e3 100644
--- a/src/openpower/decoder/selectable_int.py
+++ b/src/openpower/decoder/selectable_int.py
@@ -7,13 +7,14 @@ from operator import (add, sub, mul, floordiv, truediv, mod, or_, and_, xor,
                       neg, inv, lshift, rshift, lt, eq)
 from openpower.util import log
 
+EFFECTIVELY_UNLIMITED = 1024
 
 def check_extsign(a, b):
     if isinstance(b, FieldSelectableInt):
         b = b.get_range()
     if isinstance(b, int):
         return SelectableInt(b, a.bits)
-    if b.bits != 256:
+    if b.bits != EFFECTIVELY_UNLIMITED:
         return b
     return SelectableInt(b.value, a.bits)
 
@@ -312,7 +313,7 @@ class SelectableInt:
     def __rsub__(self, b):
         log("rsub", b, self.value)
         if isinstance(b, int):
-            b = SelectableInt(b, 256) # max extent
+            b = SelectableInt(b, EFFECTIVELY_UNLIMITED) # max extent
         #b = check_extsign(self, b)
         #assert b.bits == self.bits
         return SelectableInt(b.value - self.value, b.bits)