From: lkcl <lkcl@web>
Date: Thu, 5 May 2022 16:18:16 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2436
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=497dbefea2be9150455d9e7e8322c48e4bb98a27;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index b8e13be08..a862bb3b8 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -81,9 +81,12 @@ simplifications that went into the RISC-V ISA have an
 irrevocably damaging effect
 on its viability for high performance use.  That is not to say that
 its use in low-performance embedded scenarios is not ideal: in
-private custom secretive commercial usage it is perfect. Ubiquitous
+private custom secretive commercial usage it is perfect.
+Trinamic, an early adopter, created their TMC2660 Stepper IC
+replacing ARM with RISC-V and saving themselves USD 1 in licensing
+royalties per product are a classic case study.  Ubiquitous
 and common everyday usage in scenarios currently occupied by ARM, Intel,
-AMD and IBM? not so much. Thus, even though RISC-V has Cray-style Vectors,
+AMD and IBM? not so much. Even though RISC-V has Cray-style Vectors,
 the whole ISA is, unfortunately, fundamentally flawed as far as power
 efficient high performance is concerned.