From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 19 Jun 2022 15:08:03 +0000 (+0100)
Subject: extend minor_22.csv bitsel pattern to cover bits 21..31
X-Git-Tag: sv_maxu_works-initial~383
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=498ad981fb4309d8865cc7f238078430030d89cc;p=openpower-isa.git

extend minor_22.csv bitsel pattern to cover bits 21..31
---

diff --git a/openpower/isatables/minor_22.csv b/openpower/isatables/minor_22.csv
index dc71b6bf..6e2b0c64 100644
--- a/openpower/isatables/minor_22.csv
+++ b/openpower/isatables/minor_22.csv
@@ -1,5 +1,5 @@
 opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS,unofficial,comment2
-11011-,VL,OP_SETVL,RA_OR_ZERO,NONE,NONE,RT_OR_ZERO,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,setvl,SVL,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-011001,VL,OP_SVSHAPE,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,svshape,SVM,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-111001,VL,OP_SVREMAP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,svremap,SVRM,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-10011-,VL,OP_SVSTEP,NONE,NONE,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,svstep,SVL,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+-----11011-,VL,OP_SETVL,RA_OR_ZERO,NONE,NONE,RT_OR_ZERO,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,setvl,SVL,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+-----011001,VL,OP_SVSHAPE,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,svshape,SVM,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+-----111001,VL,OP_SVREMAP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,svremap,SVRM,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+-----10011-,VL,OP_SVSTEP,NONE,NONE,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,svstep,SVL,,1,unofficial until submitted and approved/renumbered by the opf isa wg
diff --git a/src/openpower/decoder/power_decoder.py b/src/openpower/decoder/power_decoder.py
index 72fc85c9..2b4799c6 100644
--- a/src/openpower/decoder/power_decoder.py
+++ b/src/openpower/decoder/power_decoder.py
@@ -93,7 +93,7 @@ from nmigen import Module, Elaboratable, Signal, Cat, Mux, Const
 from nmigen.cli import rtlil, verilog
 from openpower.decoder.power_enums import (Function, Form, MicrOp,
                                            In1Sel, In2Sel, In3Sel, OutSel,
-                                           SVEXTRA, SVEtype, SVPtype,  # Simple-V
+                                           SVEXTRA, SVEtype, SVPtype, # Simple-V
                                            RC, LdstLen, LDSTMode, CryIn,
                                            single_bit_flags, CRInSel,
                                            CROutSel, get_signal_name,
@@ -113,7 +113,7 @@ Subdecoder = namedtuple(  # fix autoformatter
      "opcodes",    # a dictionary of minor patterns to find
      "opint",      # true => the pattern must not be in "10----11" format
      # the bits (as a range) against which "pattern" matches
-     "bitsel",
+     "bitsel",     # should be in MSB0 order but isn't! it's LSB0. um.
      "suffix",     # shift the opcode down before decoding
      "subdecoders"  # list of further subdecoders for *additional* matches,
      # *ONLY* after "pattern" has *ALSO* been matched against.
@@ -704,6 +704,8 @@ def create_pdecode(name=None, col_subset=None, row_subset=None,
     """create_pdecode - creates a cascading hierarchical POWER ISA decoder
 
     subsetting of the PowerOp decoding is possible by setting col_subset
+
+    NOTE (sigh) the bitsel patterns are in LSB0 order, they should be MSB0
     """
     log("create_pdecode", name, col_subset, row_subset, include_fp)
 
@@ -735,7 +737,7 @@ def create_pdecode(name=None, col_subset=None, row_subset=None,
         Subdecoder(pattern=62, opcodes=get_csv("minor_62.csv"),
                    opint=True, bitsel=(0, 2), suffix=None, subdecoders=[]),
         Subdecoder(pattern=22, opcodes=get_csv("minor_22.csv"),
-                   opint=False, bitsel=(0, 6), suffix=None, subdecoders=[]),
+                   opint=False, bitsel=(0, 11), suffix=None, subdecoders=[]),
         Subdecoder(pattern=5, opcodes=get_csv("minor_5.csv"),
                    opint=True, bitsel=(0, 11), suffix=None, subdecoders=[]),
     ]