From: lkcl <lkcl@web>
Date: Mon, 10 Oct 2022 19:32:25 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~97
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=498f9f56fa54e7a34a4a89f7e7bb585848f675f8;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls002/discussion.mdwn b/openpower/sv/rfc/ls002/discussion.mdwn
index 10b312e4a..91e27fa34 100644
--- a/openpower/sv/rfc/ls002/discussion.mdwn
+++ b/openpower/sv/rfc/ls002/discussion.mdwn
@@ -165,7 +165,7 @@ would require more instructions, where `flis` is not.
 6. The RTL for fmvis should use left arrow for assignment.
 **
 
-RTL error corrected. ack on FRT.
+RTL error corrected. ack on FRT. done.
 
 **
 7. The architecture spec (VSX chapter) uses "BFP32" and "BFP64", and the
@@ -182,7 +182,7 @@ acknowledged. done.
    spec.
 **
 
-yes Paul kindly gave advice on that.
+yes Paul kindly gave advice on that. done.
 
 **
 9. In the first clause of the verbal description of fishmv I think "inserted
@@ -192,7 +192,7 @@ yes Paul kindly gave advice on that.
    paragraph.
 **
 
-ack. TODO.
+ack. done. (actually, removed the duplicate sentence/phrase)
 
 **
 10. The paragraph before the Programming Note in the fishmv description