From: Rob Clark Date: Wed, 12 Sep 2018 19:54:47 +0000 (-0400) Subject: freedreno/a6xx: fix shaders w/ >= 24 regs X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=49d22c2dfcebb794a0bc7d481ac11f8817e214b6;p=mesa.git freedreno/a6xx: fix shaders w/ >= 24 regs Possibly these bits mean something else now. Blob always seems to use FOUR_QUADS, and changing to TWO_QUADS seems to cause different threads to overlap registers. Signed-off-by: Rob Clark --- diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c index b2354de7e30..6ce02d63210 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c @@ -310,7 +310,7 @@ fd6_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring, setup_stages(emit, s); - fssz = (s[FS].i->max_reg >= 24) ? TWO_QUADS : FOUR_QUADS; + fssz = FOUR_QUADS; pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS); psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);