From: Florent Kermarrec Date: Mon, 13 Apr 2015 11:25:27 +0000 (+0200) Subject: litescope: pep8 (E203) X-Git-Tag: 24jan2021_ls180~2357 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=49dcf8d83117e2f40f5a9ed9c7de3aa357dfc287;p=litex.git litescope: pep8 (E203) --- diff --git a/misoclib/tools/litescope/bridge/uart2wb.py b/misoclib/tools/litescope/bridge/uart2wb.py index 83968255..2a494147 100644 --- a/misoclib/tools/litescope/bridge/uart2wb.py +++ b/misoclib/tools/litescope/bridge/uart2wb.py @@ -47,8 +47,8 @@ class UARTMux(Module): class LiteScopeUART2WB(Module, AutoCSR): cmds = { - "write" : 0x01, - "read" : 0x02 + "write": 0x01, + "read": 0x02 } def __init__(self, pads, clk_freq, baudrate=115200, share_uart=False): self.wishbone = wishbone.Interface() diff --git a/misoclib/tools/litescope/host/driver/uart.py b/misoclib/tools/litescope/host/driver/uart.py index 9a0b65bb..877e7bf2 100644 --- a/misoclib/tools/litescope/host/driver/uart.py +++ b/misoclib/tools/litescope/host/driver/uart.py @@ -9,8 +9,8 @@ def write_b(uart, data): class LiteScopeUARTDriver: cmds = { - "write" : 0x01, - "read" : 0x02 + "write": 0x01, + "read": 0x02 } def __init__(self, port, baudrate=115200, addrmap=None, busword=8, debug=False): self.port = port diff --git a/misoclib/tools/litescope/host/dump/__init__.py b/misoclib/tools/litescope/host/dump/__init__.py index 2b562ae0..84a9896e 100644 --- a/misoclib/tools/litescope/host/dump/__init__.py +++ b/misoclib/tools/litescope/host/dump/__init__.py @@ -77,7 +77,7 @@ class Var: def change(self, cnt): r = "" - try : + try: if self.values[cnt+1] != self.val: r += "b" r += dec2bin(self.values[cnt+1], self.width) @@ -85,7 +85,7 @@ class Var: r += self.vcd_id r += "\n" return r - except : + except: return r return r