From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 21 Feb 2015 14:01:13 +0000 (+0100)
Subject: Fixed "flatten" for non-pre-derived modules
X-Git-Tag: yosys-0.6~403
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=49dd9c713f008173100e159782223aede631b510;p=yosys.git

Fixed "flatten" for non-pre-derived modules
---

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 8435d3a32..87e736bda 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -1088,7 +1088,7 @@ struct FlattenPass : public Pass {
 				if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, false))
 					did_something = true;
 			} else {
-				for (auto mod : design->modules())
+				for (auto mod : vector<Module*>(design->modules()))
 					if (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false))
 						did_something = true;
 			}
@@ -1098,7 +1098,7 @@ struct FlattenPass : public Pass {
 
 		if (top_mod != NULL) {
 			dict<RTLIL::IdString, RTLIL::Module*> new_modules;
-			for (auto mod : design->modules())
+			for (auto mod : vector<Module*>(design->modules()))
 				if (mod == top_mod || mod->get_bool_attribute("\\blackbox")) {
 					new_modules[mod->name] = mod;
 				} else {