From: Tom Stellard Date: Mon, 28 May 2012 02:11:53 +0000 (-0400) Subject: radeon/llvm: Remove AMDILTargetMachine X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=49fb99bd131a4ed89e6f55cf360f67618acafec4;p=mesa.git radeon/llvm: Remove AMDILTargetMachine --- diff --git a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp index 5c4d82b6597..0601fbc0aa6 100644 --- a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp +++ b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp @@ -14,7 +14,6 @@ #include "AMDGPUTargetMachine.h" #include "AMDGPU.h" -#include "AMDILTargetMachine.h" #include "R600ISelLowering.h" #include "R600InstrInfo.h" #include "SIISelLowering.h" @@ -33,6 +32,11 @@ using namespace llvm; +extern "C" void LLVMInitializeAMDGPUTarget() { + // Register the target + RegisterTargetMachine X(TheAMDGPUTarget); +} + AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, TargetOptions Options, @@ -40,8 +44,12 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT, CodeGenOpt::Level OptLevel ) : - AMDILTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel), + LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel), Subtarget(TT, CPU, FS), + DataLayout(Subtarget.getDataLayout()), + FrameLowering(TargetFrameLowering::StackGrowsUp, + Subtarget.device()->getStackAlignment(), 0), + IntrinsicInfo(this), mDump(false) { diff --git a/src/gallium/drivers/radeon/AMDGPUTargetMachine.h b/src/gallium/drivers/radeon/AMDGPUTargetMachine.h index 2f60e76299b..84a1ea330d3 100644 --- a/src/gallium/drivers/radeon/AMDGPUTargetMachine.h +++ b/src/gallium/drivers/radeon/AMDGPUTargetMachine.h @@ -15,7 +15,9 @@ #define AMDGPU_TARGET_MACHINE_H #include "AMDGPUInstrInfo.h" -#include "AMDILTargetMachine.h" +#include "AMDILFrameLowering.h" +#include "AMDILIntrinsicInfo.h" +#include "AMDILSubtarget.h" #include "R600ISelLowering.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/Target/TargetData.h" @@ -24,13 +26,15 @@ namespace llvm { MCAsmInfo* createMCAsmInfo(const Target &T, StringRef TT); -class AMDGPUTargetMachine : public AMDILTargetMachine { +class AMDGPUTargetMachine : public LLVMTargetMachine { + AMDILSubtarget Subtarget; - const AMDGPUInstrInfo * InstrInfo; - AMDGPUTargetLowering * TLInfo; - AMDILGlobalManager *mGM; - AMDILKernelManager *mKM; - bool mDump; + const TargetData DataLayout; + AMDILFrameLowering FrameLowering; + AMDILIntrinsicInfo IntrinsicInfo; + const AMDGPUInstrInfo * InstrInfo; + AMDGPUTargetLowering * TLInfo; + bool mDump; public: AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef FS, @@ -39,6 +43,12 @@ public: Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); ~AMDGPUTargetMachine(); + virtual const AMDILFrameLowering* getFrameLowering() const { + return &FrameLowering; + } + virtual const AMDILIntrinsicInfo* getIntrinsicInfo() const { + return &IntrinsicInfo; + } virtual const AMDGPUInstrInfo *getInstrInfo() const {return InstrInfo;} virtual const AMDILSubtarget *getSubtargetImpl() const {return &Subtarget; } virtual const AMDGPURegisterInfo *getRegisterInfo() const { @@ -47,6 +57,7 @@ public: virtual AMDGPUTargetLowering * getTargetLowering() const { return TLInfo; } + virtual const TargetData* getTargetData() const { return &DataLayout; } virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); virtual bool addPassesToEmitFile(PassManagerBase &PM, formatted_raw_ostream &Out, diff --git a/src/gallium/drivers/radeon/AMDIL.h b/src/gallium/drivers/radeon/AMDIL.h index 769c98506e0..45638f64280 100644 --- a/src/gallium/drivers/radeon/AMDIL.h +++ b/src/gallium/drivers/radeon/AMDIL.h @@ -82,7 +82,6 @@ const unsigned int RESERVED_FUNCS = 1024; namespace llvm { class AMDILInstrPrinter; -class AMDILTargetMachine; class FunctionPass; class MCAsmInfo; class raw_ostream; @@ -91,7 +90,7 @@ class TargetMachine; /// Instruction selection passes. FunctionPass* - createAMDILISelDag(AMDILTargetMachine &TM AMDIL_OPT_LEVEL_DECL); + createAMDILISelDag(TargetMachine &TM AMDIL_OPT_LEVEL_DECL); FunctionPass* createAMDILPeepholeOpt(TargetMachine &TM AMDIL_OPT_LEVEL_DECL); diff --git a/src/gallium/drivers/radeon/AMDILCFGStructurizer.cpp b/src/gallium/drivers/radeon/AMDILCFGStructurizer.cpp index cdcd5e89880..e47c2d8faa3 100644 --- a/src/gallium/drivers/radeon/AMDILCFGStructurizer.cpp +++ b/src/gallium/drivers/radeon/AMDILCFGStructurizer.cpp @@ -10,7 +10,8 @@ #define DEBUGME 0 #define DEBUG_TYPE "structcfg" -#include "AMDILTargetMachine.h" +#include "AMDIL.h" +#include "AMDILRegisterInfo.h" #include "AMDILUtilityFunctions.h" #include "llvm/ADT/SCCIterator.h" #include "llvm/ADT/SmallVector.h" @@ -23,9 +24,11 @@ #include "llvm/CodeGen/MachineFunctionAnalysis.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineJumpTableInfo.h" #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/Target/TargetInstrInfo.h" #define FirstNonDebugInstr(A) A->begin() using namespace llvm; diff --git a/src/gallium/drivers/radeon/AMDILISelDAGToDAG.cpp b/src/gallium/drivers/radeon/AMDILISelDAGToDAG.cpp index a96cc9507a3..b08e97b02b8 100644 --- a/src/gallium/drivers/radeon/AMDILISelDAGToDAG.cpp +++ b/src/gallium/drivers/radeon/AMDILISelDAGToDAG.cpp @@ -12,7 +12,6 @@ //===----------------------------------------------------------------------===// #include "AMDGPUISelLowering.h" // For AMDGPUISD #include "AMDILDevices.h" -#include "AMDILTargetMachine.h" #include "AMDILUtilityFunctions.h" #include "llvm/ADT/ValueMap.h" #include "llvm/CodeGen/PseudoSourceValue.h" @@ -37,7 +36,7 @@ class AMDILDAGToDAGISel : public SelectionDAGISel { // make the right decision when generating code for different targets. const AMDILSubtarget &Subtarget; public: - AMDILDAGToDAGISel(AMDILTargetMachine &TM AMDIL_OPT_LEVEL_DECL); + AMDILDAGToDAGISel(TargetMachine &TM AMDIL_OPT_LEVEL_DECL); virtual ~AMDILDAGToDAGISel(); SDNode *Select(SDNode *N); @@ -76,12 +75,12 @@ private: // createAMDILISelDag - This pass converts a legalized DAG into a AMDIL-specific // DAG, ready for instruction scheduling. // -FunctionPass *llvm::createAMDILISelDag(AMDILTargetMachine &TM +FunctionPass *llvm::createAMDILISelDag(TargetMachine &TM AMDIL_OPT_LEVEL_DECL) { return new AMDILDAGToDAGISel(TM AMDIL_OPT_LEVEL_VAR); } -AMDILDAGToDAGISel::AMDILDAGToDAGISel(AMDILTargetMachine &TM +AMDILDAGToDAGISel::AMDILDAGToDAGISel(TargetMachine &TM AMDIL_OPT_LEVEL_DECL) : SelectionDAGISel(TM AMDIL_OPT_LEVEL_VAR), Subtarget(TM.getSubtarget()) { diff --git a/src/gallium/drivers/radeon/AMDILISelLowering.cpp b/src/gallium/drivers/radeon/AMDILISelLowering.cpp index 92cf9d60b64..27cf9b16efb 100644 --- a/src/gallium/drivers/radeon/AMDILISelLowering.cpp +++ b/src/gallium/drivers/radeon/AMDILISelLowering.cpp @@ -15,8 +15,8 @@ #include "AMDILISelLowering.h" #include "AMDILDevices.h" #include "AMDILIntrinsicInfo.h" +#include "AMDILRegisterInfo.h" #include "AMDILSubtarget.h" -#include "AMDILTargetMachine.h" #include "AMDILUtilityFunctions.h" #include "llvm/CallingConv.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -29,6 +29,7 @@ #include "llvm/Instructions.h" #include "llvm/Intrinsics.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetOptions.h" using namespace llvm; @@ -585,25 +586,24 @@ AMDILTargetLowering::convertToReg(MachineOperand op) const size_t numIntTypes = sizeof(IntTypes) / sizeof(*IntTypes); size_t numVectorTypes = sizeof(VectorTypes) / sizeof(*VectorTypes); - const AMDILSubtarget *stm = reinterpret_cast( - &this->getTargetMachine())->getSubtargetImpl(); + const AMDILSubtarget &STM = getTargetMachine().getSubtarget(); // These are the current register classes that are // supported addRegisterClass(MVT::i32, AMDIL::GPRI32RegisterClass); addRegisterClass(MVT::f32, AMDIL::GPRF32RegisterClass); - if (stm->device()->isSupported(AMDILDeviceInfo::DoubleOps)) { + if (STM.device()->isSupported(AMDILDeviceInfo::DoubleOps)) { addRegisterClass(MVT::f64, AMDIL::GPRF64RegisterClass); addRegisterClass(MVT::v2f64, AMDIL::GPRV2F64RegisterClass); } - if (stm->device()->isSupported(AMDILDeviceInfo::ByteOps)) { + if (STM.device()->isSupported(AMDILDeviceInfo::ByteOps)) { addRegisterClass(MVT::i8, AMDIL::GPRI8RegisterClass); addRegisterClass(MVT::v2i8, AMDIL::GPRV2I8RegisterClass); addRegisterClass(MVT::v4i8, AMDIL::GPRV4I8RegisterClass); setOperationAction(ISD::Constant , MVT::i8 , Legal); } - if (stm->device()->isSupported(AMDILDeviceInfo::ShortOps)) { + if (STM.device()->isSupported(AMDILDeviceInfo::ShortOps)) { addRegisterClass(MVT::i16, AMDIL::GPRI16RegisterClass); addRegisterClass(MVT::v2i16, AMDIL::GPRV2I16RegisterClass); addRegisterClass(MVT::v4i16, AMDIL::GPRV4I16RegisterClass); @@ -613,7 +613,7 @@ AMDILTargetLowering::convertToReg(MachineOperand op) const addRegisterClass(MVT::v4f32, AMDIL::GPRV4F32RegisterClass); addRegisterClass(MVT::v2i32, AMDIL::GPRV2I32RegisterClass); addRegisterClass(MVT::v4i32, AMDIL::GPRV4I32RegisterClass); - if (stm->device()->isSupported(AMDILDeviceInfo::LongOps)) { + if (STM.device()->isSupported(AMDILDeviceInfo::LongOps)) { addRegisterClass(MVT::i64, AMDIL::GPRI64RegisterClass); addRegisterClass(MVT::v2i64, AMDIL::GPRV2I64RegisterClass); } @@ -712,9 +712,9 @@ AMDILTargetLowering::convertToReg(MachineOperand op) const } setOperationAction(ISD::FP_ROUND, MVT::Other, Expand); - if (stm->device()->isSupported(AMDILDeviceInfo::LongOps)) { - if (stm->calVersion() < CAL_VERSION_SC_139 - || stm->device()->getGeneration() == AMDILDeviceInfo::HD4XXX) { + if (STM.device()->isSupported(AMDILDeviceInfo::LongOps)) { + if (STM.calVersion() < CAL_VERSION_SC_139 + || STM.device()->getGeneration() == AMDILDeviceInfo::HD4XXX) { setOperationAction(ISD::MUL, MVT::i64, Custom); } setOperationAction(ISD::SUB, MVT::i64, Custom); @@ -736,7 +736,7 @@ AMDILTargetLowering::convertToReg(MachineOperand op) const setOperationAction(ISD::ZERO_EXTEND, MVT::v2i64, Expand); setOperationAction(ISD::ANY_EXTEND, MVT::v2i64, Expand); } - if (stm->device()->isSupported(AMDILDeviceInfo::DoubleOps)) { + if (STM.device()->isSupported(AMDILDeviceInfo::DoubleOps)) { // we support loading/storing v2f64 but not operations on the type setOperationAction(ISD::FADD, MVT::v2f64, Expand); setOperationAction(ISD::FSUB, MVT::v2f64, Expand); @@ -1979,9 +1979,8 @@ AMDILTargetLowering::genCLZu32(SDValue Op, SelectionDAG &DAG) const SDValue DST = SDValue(); DebugLoc DL = Op.getDebugLoc(); EVT INTTY = Op.getValueType(); - const AMDILSubtarget *stm = reinterpret_cast( - &this->getTargetMachine())->getSubtargetImpl(); - if (stm->device()->getGeneration() >= AMDILDeviceInfo::HD5XXX) { + const AMDILSubtarget &STM = getTargetMachine().getSubtarget(); + if (STM.device()->getGeneration() >= AMDILDeviceInfo::HD5XXX) { //__clz_32bit(uint u) //{ // int z = __amdil_ffb_hi(u) ; @@ -1998,7 +1997,7 @@ AMDILTargetLowering::genCLZu32(SDValue Op, SelectionDAG &DAG) const // return cmp ? 32 : z DST = DAG.getNode(AMDILISD::CMOVLOG, DL, INTTY, cmp, DAG.getConstant(32, INTTY), z); - } else if (stm->device()->getGeneration() == AMDILDeviceInfo::HD4XXX) { + } else if (STM.device()->getGeneration() == AMDILDeviceInfo::HD4XXX) { // static inline uint //__clz_32bit(uint x) //{ @@ -2048,9 +2047,8 @@ AMDILTargetLowering::genCLZu64(SDValue Op, SelectionDAG &DAG) const } else { INTTY = EVT(MVT::i32); } - const AMDILSubtarget *stm = reinterpret_cast( - &this->getTargetMachine())->getSubtargetImpl(); - if (stm->device()->getGeneration() >= AMDILDeviceInfo::HD5XXX) { + const AMDILSubtarget &STM = getTargetMachine().getSubtarget(); + if (STM.device()->getGeneration() >= AMDILDeviceInfo::HD5XXX) { // Evergreen: // static inline uint // __clz_u64(ulong x) @@ -2078,7 +2076,7 @@ AMDILTargetLowering::genCLZu64(SDValue Op, SelectionDAG &DAG) const DAG.getConstant(32U, INTTY), zlo); // return cmp ? zlop32: zhi DST = DAG.getNode(AMDILISD::CMOVLOG, DL, INTTY, cmp, zlop32, zhi); - } else if (stm->device()->getGeneration() == AMDILDeviceInfo::HD4XXX) { + } else if (STM.device()->getGeneration() == AMDILDeviceInfo::HD4XXX) { // HD4XXX: // static inline uint //__clz_64bit(ulong x) @@ -2164,9 +2162,8 @@ AMDILTargetLowering::genf64toi64(SDValue RHS, SelectionDAG &DAG, LONGVT = EVT(MVT::i64); INTVT = EVT(MVT::i32); } - const AMDILSubtarget *stm = reinterpret_cast( - &this->getTargetMachine())->getSubtargetImpl(); - if (stm->device()->getGeneration() > AMDILDeviceInfo::HD6XXX) { + const AMDILSubtarget &STM = getTargetMachine().getSubtarget(); + if (STM.device()->getGeneration() > AMDILDeviceInfo::HD6XXX) { // unsigned version: // uint uhi = (uint)(d * 0x1.0p-32); // uint ulo = (uint)(mad((double)uhi, -0x1.0p+32, d)); @@ -2428,14 +2425,9 @@ AMDILTargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const EVT LHSVT = Op.getValueType(); MVT LST = LHSVT.getScalarType().getSimpleVT(); DebugLoc DL = Op.getDebugLoc(); - const AMDILTargetMachine* - amdtm = reinterpret_cast - (&this->getTargetMachine()); - const AMDILSubtarget* - stm = static_cast( - amdtm->getSubtargetImpl()); + const AMDILSubtarget &STM = getTargetMachine().getSubtarget(); if (RST == MVT::f64 && RHSVT.isVector() - && stm->device()->getGeneration() > AMDILDeviceInfo::HD6XXX) { + && STM.device()->getGeneration() > AMDILDeviceInfo::HD6XXX) { // We dont support vector 64bit floating point convertions. for (unsigned x = 0, y = RHSVT.getVectorNumElements(); x < y; ++x) { SDValue op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, @@ -2452,7 +2444,7 @@ AMDILTargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const } else { if (RST == MVT::f64 && LST == MVT::i32) { - if (stm->device()->getGeneration() > AMDILDeviceInfo::HD6XXX) { + if (STM.device()->getGeneration() > AMDILDeviceInfo::HD6XXX) { DST = SDValue(Op.getNode(), 0); } else { DST = genf64toi32(RHS, DAG, false); @@ -2462,7 +2454,7 @@ AMDILTargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const DST = genf64toi64(RHS, DAG, false); } else if (RST == MVT::f64 && (LST == MVT::i8 || LST == MVT::i16)) { - if (stm->device()->getGeneration() > AMDILDeviceInfo::HD6XXX) { + if (STM.device()->getGeneration() > AMDILDeviceInfo::HD6XXX) { DST = DAG.getNode(ISD::TRUNCATE, DL, LHSVT, SDValue(Op.getNode(), 0)); } else { SDValue ToInt = genf64toi32(RHS, DAG, false); @@ -2494,13 +2486,8 @@ AMDILTargetLowering::genu32tof64(SDValue RHS, EVT LHSVT, INTVT = EVT(MVT::i32); } SDValue x = RHS; - const AMDILTargetMachine* - amdtm = reinterpret_cast - (&this->getTargetMachine()); - const AMDILSubtarget* - stm = static_cast( - amdtm->getSubtargetImpl()); - if (stm->calVersion() >= CAL_VERSION_SC_135) { + const AMDILSubtarget &STM = getTargetMachine().getSubtarget(); + if (STM.calVersion() >= CAL_VERSION_SC_135) { // unsigned x = RHS; // ulong xd = (ulong)(0x4330_0000 << 32) | x; // double d = as_double( xd ); @@ -2558,9 +2545,8 @@ AMDILTargetLowering::genu64tof64(SDValue RHS, EVT LHSVT, } LONGVT = RHSVT; SDValue x = RHS; - const AMDILSubtarget *stm = reinterpret_cast( - &this->getTargetMachine())->getSubtargetImpl(); - if (stm->device()->getGeneration() > AMDILDeviceInfo::HD6XXX) { + const AMDILSubtarget &STM = getTargetMachine().getSubtarget(); + if (STM.device()->getGeneration() > AMDILDeviceInfo::HD6XXX) { // double dhi = (double)(as_uint2(x).y); // double dlo = (double)(as_uint2(x).x); // return mad(dhi, 0x1.0p+32, dlo) @@ -2570,7 +2556,7 @@ AMDILTargetLowering::genu64tof64(SDValue RHS, EVT LHSVT, dlo = DAG.getNode(ISD::UINT_TO_FP, DL, LHSVT, dlo); return DAG.getNode(AMDILISD::MAD, DL, LHSVT, dhi, DAG.getConstantFP(0x4f800000, LHSVT), dlo); - } else if (stm->calVersion() >= CAL_VERSION_SC_135) { + } else if (STM.calVersion() >= CAL_VERSION_SC_135) { // double lo = as_double( as_ulong( 0x1.0p+52) | (u & 0xffff_ffffUL)); // double hi = as_double( as_ulong( 0x1.0p+84) | (u >> 32)); // return (hi - (0x1.0p+84 + 0x1.0p+52)) + lo; @@ -2669,14 +2655,9 @@ AMDILTargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const SDValue DST; EVT INTVT; EVT LONGVT; - const AMDILTargetMachine* - amdtm = reinterpret_cast - (&this->getTargetMachine()); - const AMDILSubtarget* - stm = static_cast( - amdtm->getSubtargetImpl()); + const AMDILSubtarget &STM = getTargetMachine().getSubtarget(); if (LST == MVT::f64 && LHSVT.isVector() - && stm->device()->getGeneration() > AMDILDeviceInfo::HD6XXX) { + && STM.device()->getGeneration() > AMDILDeviceInfo::HD6XXX) { // We dont support vector 64bit floating point convertions. DST = Op; for (unsigned x = 0, y = LHSVT.getVectorNumElements(); x < y; ++x) { @@ -2695,7 +2676,7 @@ AMDILTargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const if (RST == MVT::i32 && LST == MVT::f64) { - if (stm->device()->getGeneration() > AMDILDeviceInfo::HD6XXX) { + if (STM.device()->getGeneration() > AMDILDeviceInfo::HD6XXX) { DST = SDValue(Op.getNode(), 0); } else { DST = genu32tof64(RHS, LHSVT, DAG); @@ -2720,12 +2701,6 @@ AMDILTargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const SDValue DST; bool isVec = RHS.getValueType().isVector(); if (OVT.getScalarType() == MVT::i64) { - /*const AMDILTargetMachine* - amdtm = reinterpret_cast - (&this->getTargetMachine()); - const AMDILSubtarget* - stm = dynamic_cast( - amdtm->getSubtargetImpl());*/ MVT INTTY = MVT::i32; if (OVT == MVT::v2i64) { INTTY = MVT::v2i32; @@ -3941,9 +3916,8 @@ AMDILTargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const SDValue LHS = Op.getOperand(0); SDValue RHS = Op.getOperand(1); SDValue DST; - const AMDILSubtarget *stm = reinterpret_cast( - &this->getTargetMachine())->getSubtargetImpl(); - if (stm->device()->getGeneration() == AMDILDeviceInfo::HD4XXX) { + const AMDILSubtarget &STM = getTargetMachine().getSubtarget(); + if (STM.device()->getGeneration() == AMDILDeviceInfo::HD4XXX) { // TODO: This doesn't work for vector types yet // The LowerFDIV32 function generates equivalent to the following // IL: diff --git a/src/gallium/drivers/radeon/AMDILInstrInfo.cpp b/src/gallium/drivers/radeon/AMDILInstrInfo.cpp index cd2fb48209c..8e27ae3433a 100644 --- a/src/gallium/drivers/radeon/AMDILInstrInfo.cpp +++ b/src/gallium/drivers/radeon/AMDILInstrInfo.cpp @@ -26,7 +26,7 @@ using namespace llvm; -AMDILInstrInfo::AMDILInstrInfo(AMDILTargetMachine &tm) +AMDILInstrInfo::AMDILInstrInfo(TargetMachine &tm) : AMDILGenInstrInfo(AMDIL::ADJCALLSTACKDOWN, AMDIL::ADJCALLSTACKUP), RI(tm, *this), TM(tm) { diff --git a/src/gallium/drivers/radeon/AMDILInstrInfo.h b/src/gallium/drivers/radeon/AMDILInstrInfo.h index 4121246e6f9..9de16ed8e59 100644 --- a/src/gallium/drivers/radeon/AMDILInstrInfo.h +++ b/src/gallium/drivers/radeon/AMDILInstrInfo.h @@ -28,12 +28,12 @@ namespace llvm { class AMDILInstrInfo : public AMDILGenInstrInfo { private: const AMDILRegisterInfo RI; - AMDILTargetMachine &TM; + TargetMachine &TM; bool getNextBranchInstr(MachineBasicBlock::iterator &iter, MachineBasicBlock &MBB) const; unsigned int getBranchInstr(const MachineOperand &op) const; public: - explicit AMDILInstrInfo(AMDILTargetMachine &tm); + explicit AMDILInstrInfo(TargetMachine &tm); // getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As // such, whenever a client has an instance of instruction info, it should diff --git a/src/gallium/drivers/radeon/AMDILIntrinsicInfo.cpp b/src/gallium/drivers/radeon/AMDILIntrinsicInfo.cpp index 75729ac01a3..566a91e48f3 100644 --- a/src/gallium/drivers/radeon/AMDILIntrinsicInfo.cpp +++ b/src/gallium/drivers/radeon/AMDILIntrinsicInfo.cpp @@ -13,7 +13,7 @@ #include "AMDILIntrinsicInfo.h" #include "AMDIL.h" -#include "AMDILTargetMachine.h" +#include "AMDILSubtarget.h" #include "llvm/DerivedTypes.h" #include "llvm/Intrinsics.h" #include "llvm/Module.h" @@ -24,7 +24,7 @@ using namespace llvm; #include "AMDILGenIntrinsics.inc" #undef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN -AMDILIntrinsicInfo::AMDILIntrinsicInfo(AMDILTargetMachine *tm) +AMDILIntrinsicInfo::AMDILIntrinsicInfo(TargetMachine *tm) : TargetIntrinsicInfo(), mTM(tm) { } @@ -176,7 +176,7 @@ AMDILIntrinsicInfo::getDeclaration(Module *M, unsigned IntrID, bool AMDILIntrinsicInfo::isValidIntrinsic(unsigned int IntrID) const { - const AMDILSubtarget *stm = mTM->getSubtargetImpl(); + const AMDILSubtarget &STM = mTM->getSubtarget(); switch (IntrID) { default: return true; @@ -185,6 +185,6 @@ AMDILIntrinsicInfo::isValidIntrinsic(unsigned int IntrID) const case AMDGPUIntrinsic::AMDIL_convert_f32_f16_near: case AMDGPUIntrinsic::AMDIL_convert_f32_f16_neg_inf: case AMDGPUIntrinsic::AMDIL_convert_f32_f16_plus_inf: - return stm->calVersion() >= CAL_VERSION_SC_139; + return STM.calVersion() >= CAL_VERSION_SC_139; }; } diff --git a/src/gallium/drivers/radeon/AMDILIntrinsicInfo.h b/src/gallium/drivers/radeon/AMDILIntrinsicInfo.h index 513c6f06e85..bdd0366fd1c 100644 --- a/src/gallium/drivers/radeon/AMDILIntrinsicInfo.h +++ b/src/gallium/drivers/radeon/AMDILIntrinsicInfo.h @@ -17,7 +17,7 @@ #include "llvm/Target/TargetIntrinsicInfo.h" namespace llvm { - class AMDILTargetMachine; + class TargetMachine; namespace AMDGPUIntrinsic { enum ID { last_non_AMDIL_intrinsic = Intrinsic::num_intrinsics - 1, @@ -31,9 +31,9 @@ namespace llvm { class AMDILIntrinsicInfo : public TargetIntrinsicInfo { - AMDILTargetMachine *mTM; + TargetMachine *mTM; public: - AMDILIntrinsicInfo(AMDILTargetMachine *tm); + AMDILIntrinsicInfo(TargetMachine *tm); std::string getName(unsigned int IntrId, Type **Tys = 0, unsigned int numTys = 0) const; unsigned int lookupName(const char *Name, unsigned int Len) const; diff --git a/src/gallium/drivers/radeon/AMDILRegisterInfo.cpp b/src/gallium/drivers/radeon/AMDILRegisterInfo.cpp index 453889fc8aa..9d93b91f000 100644 --- a/src/gallium/drivers/radeon/AMDILRegisterInfo.cpp +++ b/src/gallium/drivers/radeon/AMDILRegisterInfo.cpp @@ -21,14 +21,13 @@ #include "AMDILRegisterInfo.h" #include "AMDIL.h" #include "AMDILInstrInfo.h" -#include "AMDILTargetMachine.h" #include "llvm/ADT/BitVector.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" using namespace llvm; -AMDILRegisterInfo::AMDILRegisterInfo(AMDILTargetMachine &tm, +AMDILRegisterInfo::AMDILRegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii) : AMDILGenRegisterInfo(0), // RA??? TM(tm), TII(tii) diff --git a/src/gallium/drivers/radeon/AMDILRegisterInfo.h b/src/gallium/drivers/radeon/AMDILRegisterInfo.h index 5207cd8b466..8dd4281d6a5 100644 --- a/src/gallium/drivers/radeon/AMDILRegisterInfo.h +++ b/src/gallium/drivers/radeon/AMDILRegisterInfo.h @@ -23,7 +23,6 @@ namespace llvm { - class AMDILTargetMachine; class TargetInstrInfo; class Type; @@ -37,10 +36,10 @@ namespace llvm struct AMDILRegisterInfo : public AMDILGenRegisterInfo { - AMDILTargetMachine &TM; + TargetMachine &TM; const TargetInstrInfo &TII; - AMDILRegisterInfo(AMDILTargetMachine &tm, const TargetInstrInfo &tii); + AMDILRegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii); /// Code Generation virtual methods... const uint16_t * getCalleeSavedRegs(const MachineFunction *MF = 0) const; diff --git a/src/gallium/drivers/radeon/AMDILTargetMachine.cpp b/src/gallium/drivers/radeon/AMDILTargetMachine.cpp deleted file mode 100644 index c821187ed80..00000000000 --- a/src/gallium/drivers/radeon/AMDILTargetMachine.cpp +++ /dev/null @@ -1,180 +0,0 @@ -//===-- AMDILTargetMachine.cpp - Define TargetMachine for AMDIL -----------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//==-----------------------------------------------------------------------===// -// -//===----------------------------------------------------------------------===// - -#include "AMDILTargetMachine.h" -#include "AMDGPUTargetMachine.h" -#include "AMDILDevices.h" -#include "AMDILFrameLowering.h" -#include "llvm/ADT/OwningPtr.h" -#include "llvm/CodeGen/MachineFunctionAnalysis.h" -#include "llvm/CodeGen/MachineModuleInfo.h" -#include "llvm/CodeGen/Passes.h" -#include "llvm/CodeGen/SchedulerRegistry.h" -#include "llvm/MC/MCAsmInfo.h" -#include "llvm/MC/MCContext.h" -#include "llvm/MC/MCStreamer.h" -#include "llvm/Pass.h" -#include "llvm/PassManager.h" -#include "llvm/Support/FormattedStream.h" -#include "llvm/Support/TargetRegistry.h" -#include "llvm/Target/TargetData.h" -#include "llvm/Transforms/Scalar.h" - -using namespace llvm; - -extern "C" void LLVMInitializeAMDILTarget() { - // Register the target - RegisterTargetMachine X(TheAMDILTarget); - RegisterTargetMachine Y(TheAMDGPUTarget); -} - -/// AMDILTargetMachine ctor - -/// -AMDILTargetMachine::AMDILTargetMachine(const Target &T, - StringRef TT, StringRef CPU, StringRef FS, - TargetOptions Options, - Reloc::Model RM, CodeModel::Model CM, - CodeGenOpt::Level OL -) -: - LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), - Subtarget(TT, CPU, FS), - DataLayout(Subtarget.getDataLayout()), - FrameLowering(TargetFrameLowering::StackGrowsUp, - Subtarget.device()->getStackAlignment(), 0), - InstrInfo(*this), //JITInfo(*this), - TLInfo(*this), - IntrinsicInfo(this) -{ - setAsmVerbosityDefault(true); - setMCUseLoc(false); -} - -AMDILTargetLowering* -AMDILTargetMachine::getTargetLowering() const -{ - return const_cast(&TLInfo); -} - -const AMDILInstrInfo* -AMDILTargetMachine::getInstrInfo() const -{ - return &InstrInfo; -} -const AMDILFrameLowering* -AMDILTargetMachine::getFrameLowering() const -{ - return &FrameLowering; -} - -const AMDILSubtarget* -AMDILTargetMachine::getSubtargetImpl() const -{ - return &Subtarget; -} - -const AMDILRegisterInfo* -AMDILTargetMachine::getRegisterInfo() const -{ - return &InstrInfo.getRegisterInfo(); -} - -const TargetData* -AMDILTargetMachine::getTargetData() const -{ - return &DataLayout; -} - -const AMDILIntrinsicInfo* -AMDILTargetMachine::getIntrinsicInfo() const -{ - return &IntrinsicInfo; -} - - void -AMDILTargetMachine::dump(llvm::raw_ostream &O) -{ - if (!mDebugMode) { - return; - } - O << ";AMDIL Target Machine State Dump: \n"; -} - - void -AMDILTargetMachine::setDebug(bool debugMode) -{ - mDebugMode = debugMode; -} - -bool -AMDILTargetMachine::getDebug() const -{ - return mDebugMode; -} - -namespace { -class AMDILPassConfig : public TargetPassConfig { - -public: - AMDILPassConfig(AMDILTargetMachine *TM, PassManagerBase &PM) - : TargetPassConfig(TM, PM) {} - - AMDILTargetMachine &getAMDILTargetMachine() const { - return getTM(); - } - - virtual bool addPreISel(); - virtual bool addInstSelector(); - virtual bool addPreRegAlloc(); - virtual bool addPostRegAlloc(); - virtual bool addPreEmitPass(); -}; -} // End of anonymous namespace - -TargetPassConfig *AMDILTargetMachine::createPassConfig(PassManagerBase &PM) { - return new AMDILPassConfig(this, PM); -} - -bool AMDILPassConfig::addPreISel() -{ - return false; -} - -bool AMDILPassConfig::addInstSelector() -{ - PM->add(createAMDILPeepholeOpt(*TM)); - PM->add(createAMDILISelDag(getAMDILTargetMachine())); - return false; -} - -bool AMDILPassConfig::addPreRegAlloc() -{ - // If debugging, reduce code motion. Use less aggressive pre-RA scheduler - if (TM->getOptLevel() == CodeGenOpt::None) { - llvm::RegisterScheduler::setDefault(&llvm::createSourceListDAGScheduler); - } - return false; -} - -bool AMDILPassConfig::addPostRegAlloc() { - return false; // -print-machineinstr should print after this. -} - -/// addPreEmitPass - This pass may be implemented by targets that want to run -/// passes immediately before machine code is emitted. This should return -/// true if -print-machineinstrs should print out the code after the passes. -bool AMDILPassConfig::addPreEmitPass() -{ - PM->add(createAMDILCFGPreparationPass(*TM)); - PM->add(createAMDILCFGStructurizerPass(*TM)); - return true; -} - diff --git a/src/gallium/drivers/radeon/AMDILTargetMachine.h b/src/gallium/drivers/radeon/AMDILTargetMachine.h deleted file mode 100644 index 0ff3674c59e..00000000000 --- a/src/gallium/drivers/radeon/AMDILTargetMachine.h +++ /dev/null @@ -1,72 +0,0 @@ -//===-- AMDILTargetMachine.h - Define TargetMachine for AMDIL ---*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//==-----------------------------------------------------------------------===// -// -// This file declares the AMDIL specific subclass of TargetMachine. -// -//===----------------------------------------------------------------------===// - -#ifndef AMDILTARGETMACHINE_H_ -#define AMDILTARGETMACHINE_H_ - -#include "AMDILFrameLowering.h" -#include "AMDILISelLowering.h" -#include "AMDILInstrInfo.h" -#include "AMDILIntrinsicInfo.h" -#include "AMDILSubtarget.h" -#include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetMachine.h" - -namespace llvm -{ - class raw_ostream; - - class AMDILTargetMachine : public LLVMTargetMachine - { - private: - AMDILSubtarget Subtarget; - const TargetData DataLayout; // Calculates type size & alignment - AMDILFrameLowering FrameLowering; - AMDILInstrInfo InstrInfo; - AMDILTargetLowering TLInfo; - AMDILIntrinsicInfo IntrinsicInfo; - bool mDebugMode; - CodeGenOpt::Level mOptLevel; - - protected: - - public: - AMDILTargetMachine(const Target &T, - StringRef TT, StringRef CPU, StringRef FS, - TargetOptions Options, - Reloc::Model RM, CodeModel::Model CM, - CodeGenOpt::Level OL); - - // Get Target/Subtarget specific information - virtual AMDILTargetLowering* getTargetLowering() const; - virtual const AMDILInstrInfo* getInstrInfo() const; - virtual const AMDILFrameLowering* getFrameLowering() const; - virtual const AMDILSubtarget* getSubtargetImpl() const; - virtual const AMDILRegisterInfo* getRegisterInfo() const; - virtual const TargetData* getTargetData() const; - virtual const AMDILIntrinsicInfo *getIntrinsicInfo() const; - - // Pass Pipeline Configuration - virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); - - void dump(llvm::raw_ostream &O); - void setDebug(bool debugMode); - bool getDebug() const; - CodeGenOpt::Level getOptLevel() const { return mOptLevel; } - - - }; // AMDILTargetMachine - -} // end namespace llvm - -#endif // AMDILTARGETMACHINE_H_ diff --git a/src/gallium/drivers/radeon/MCTargetDesc/AMDILMCTargetDesc.cpp b/src/gallium/drivers/radeon/MCTargetDesc/AMDILMCTargetDesc.cpp index 5e60b00bf53..3488d708e8c 100644 --- a/src/gallium/drivers/radeon/MCTargetDesc/AMDILMCTargetDesc.cpp +++ b/src/gallium/drivers/radeon/MCTargetDesc/AMDILMCTargetDesc.cpp @@ -46,21 +46,16 @@ static MCCodeGenInfo *createAMDILMCCodeGenInfo(StringRef TT, Reloc::Model RM, return X; } -extern "C" void LLVMInitializeAMDILTargetMC() { +extern "C" void LLVMInitializeAMDGPUTargetMC() { - RegisterMCAsmInfo X(TheAMDILTarget); RegisterMCAsmInfo Y(TheAMDGPUTarget); - TargetRegistry::RegisterMCCodeGenInfo(TheAMDILTarget, createAMDILMCCodeGenInfo); TargetRegistry::RegisterMCCodeGenInfo(TheAMDGPUTarget, createAMDILMCCodeGenInfo); - TargetRegistry::RegisterMCInstrInfo(TheAMDILTarget, createAMDILMCInstrInfo); TargetRegistry::RegisterMCInstrInfo(TheAMDGPUTarget, createAMDILMCInstrInfo); - TargetRegistry::RegisterMCRegInfo(TheAMDILTarget, createAMDILMCRegisterInfo); TargetRegistry::RegisterMCRegInfo(TheAMDGPUTarget, createAMDILMCRegisterInfo); - TargetRegistry::RegisterMCSubtargetInfo(TheAMDILTarget, createAMDILMCSubtargetInfo); TargetRegistry::RegisterMCSubtargetInfo(TheAMDGPUTarget, createAMDILMCSubtargetInfo); } diff --git a/src/gallium/drivers/radeon/MCTargetDesc/AMDILMCTargetDesc.h b/src/gallium/drivers/radeon/MCTargetDesc/AMDILMCTargetDesc.h index 370769fea25..8951a4e6461 100644 --- a/src/gallium/drivers/radeon/MCTargetDesc/AMDILMCTargetDesc.h +++ b/src/gallium/drivers/radeon/MCTargetDesc/AMDILMCTargetDesc.h @@ -19,7 +19,6 @@ namespace llvm { class MCSubtargetInfo; class Target; -extern Target TheAMDILTarget; extern Target TheAMDGPUTarget; } // End llvm namespace diff --git a/src/gallium/drivers/radeon/Makefile.sources b/src/gallium/drivers/radeon/Makefile.sources index 099eb025d70..51eb3aecb4f 100644 --- a/src/gallium/drivers/radeon/Makefile.sources +++ b/src/gallium/drivers/radeon/Makefile.sources @@ -30,7 +30,6 @@ CPP_SOURCES := \ AMDILRegisterInfo.cpp \ AMDILSIDevice.cpp \ AMDILSubtarget.cpp \ - AMDILTargetMachine.cpp \ AMDGPUTargetMachine.cpp \ AMDGPUISelLowering.cpp \ AMDGPUConvertToISA.cpp \ diff --git a/src/gallium/drivers/radeon/TargetInfo/AMDILTargetInfo.cpp b/src/gallium/drivers/radeon/TargetInfo/AMDILTargetInfo.cpp index 5dee0cb7c05..522f591e2ef 100644 --- a/src/gallium/drivers/radeon/TargetInfo/AMDILTargetInfo.cpp +++ b/src/gallium/drivers/radeon/TargetInfo/AMDILTargetInfo.cpp @@ -16,17 +16,11 @@ using namespace llvm; -/// The target for the AMDIL backend -Target llvm::TheAMDILTarget; - /// The target for the AMDGPU backend Target llvm::TheAMDGPUTarget; /// Extern function to initialize the targets for the AMDIL backend -extern "C" void LLVMInitializeAMDILTargetInfo() { - RegisterTarget - IL(TheAMDILTarget, "amdil", "ATI graphics cards"); - +extern "C" void LLVMInitializeAMDGPUTargetInfo() { RegisterTarget R600(TheAMDGPUTarget, "r600", "AMD GPUs HD2XXX-HD6XXX"); } diff --git a/src/gallium/drivers/radeon/radeon_llvm_emit.cpp b/src/gallium/drivers/radeon/radeon_llvm_emit.cpp index ebc32106b52..89130b33157 100644 --- a/src/gallium/drivers/radeon/radeon_llvm_emit.cpp +++ b/src/gallium/drivers/radeon/radeon_llvm_emit.cpp @@ -51,9 +51,9 @@ using namespace llvm; #ifndef EXTERNAL_LLVM extern "C" { -void LLVMInitializeAMDILTargetMC(void); -void LLVMInitializeAMDILTarget(void); -void LLVMInitializeAMDILTargetInfo(void); +void LLVMInitializeAMDGPUTargetMC(void); +void LLVMInitializeAMDGPUTarget(void); +void LLVMInitializeAMDGPUTargetInfo(void); } #endif @@ -75,9 +75,9 @@ radeon_llvm_compile(LLVMModuleRef M, unsigned char ** bytes, InitializeAllTargets(); InitializeAllTargetMCs(); #else - LLVMInitializeAMDILTargetInfo(); - LLVMInitializeAMDILTarget(); - LLVMInitializeAMDILTargetMC(); + LLVMInitializeAMDGPUTargetInfo(); + LLVMInitializeAMDGPUTarget(); + LLVMInitializeAMDGPUTargetMC(); #endif std::string err; const Target * AMDGPUTarget = TargetRegistry::lookupTarget("r600", err);