From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 27 Nov 2019 06:51:16 +0000 (-0800)
Subject: Add citation
X-Git-Tag: working-ls180~942^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4a0198128eb966d00c24bd6938625892e7fd4b95;p=yosys.git

Add citation
---

diff --git a/tests/arch/xilinx/dsp_fastfir.ys b/tests/arch/xilinx/dsp_fastfir.ys
index 30e74a01b..b205d42c1 100644
--- a/tests/arch/xilinx/dsp_fastfir.ys
+++ b/tests/arch/xilinx/dsp_fastfir.ys
@@ -1,4 +1,5 @@
 read_verilog <<EOT
+// Citation https://github.com/ZipCPU/dspfilters/blob/master/rtl/fastfir.v
 module fastfir_dynamictaps(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_result);
   wire [30:0] _00_;
   wire [23:0] _01_;