From: Jim Paris <jim@jtan.com>
Date: Thu, 17 May 2018 04:09:56 +0000 (-0400)
Subject: Support SystemVerilog `` extension for macros
X-Git-Tag: yosys-0.8~90^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4a229e5b953c15ecb31945258e0ca2f7bffe8a3e;p=yosys.git

Support SystemVerilog `` extension for macros
---

diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index 00124cb42..dea22ee8a 100644
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -183,8 +183,9 @@ static std::string next_token(bool pass_newline = false)
 		const char *ok = "abcdefghijklmnopqrstuvwxyz_ABCDEFGHIJKLMNOPQRSTUVWXYZ$0123456789";
 		if (ch == '`' || strchr(ok, ch) != NULL)
 		{
+			char first = ch;
 			ch = next_char();
-			if (ch == '"') {
+			if (first == '`' && (ch == '"' || ch == '`')) {
 				token += ch;
 			} else do {
 					if (strchr(ok, ch) == NULL) {
@@ -265,6 +266,9 @@ static bool try_expand_macro(std::set<std::string> &defines_with_args,
 			}
 			insert_input(defines_map[name]);
 			return true;
+	} else if (tok == "``") {
+		// Swallow `` in macro expansion
+		return true;
 	} else return false;
 }