From: Felix Held <felix-github@felixheld.de>
Date: Fri, 12 Jan 2018 02:33:13 +0000 (+1100)
Subject: fix DDR3 on nexys_video
X-Git-Tag: 24jan2021_ls180~1764^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4a3454107ac13bdd07348fab06fb6ade3908917f;p=litex.git

fix DDR3 on nexys_video
---

diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index 77b54688..daa9c980 100755
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -97,8 +97,8 @@ class BaseSoC(SoCSDRAM):
 
         # sdram
         self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
-        self.add_constant("A7DDRPHY_BITSLIP", 3)
-        self.add_constant("A7DDRPHY_DELAY", 14)
+        self.add_constant("READ_LEVELING_BITSLIP", 3)
+        self.add_constant("READ_LEVELING_DELAY", 14)
         sdram_module = MT41K256M16(self.clk_freq, "1:4")
         self.register_sdram(self.ddrphy,
                             sdram_module.geom_settings,