From: lkcl <lkcl@web>
Date: Sat, 9 Apr 2022 21:31:13 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2814
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4a498d86d43f03a3c67a3c01f670507b624372e1;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 2f422ea59..b571d9195 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -223,6 +223,12 @@ This is equivalent to
 `llvm.masked.compressstore.*`
 followed by
 `llvm.masked.expandload.*`
+with a single instruction.
+
+This extreme power and flexibility comes down to the fact that SVP64
+is not actually a Vector ISA: it is a loop-abstraction-concept that
+is applied *in general* to Scalar operations, just like the x86
+`REP` instruction (if put on steroids).
 
 # Reduce modes