From: Florent Kermarrec Date: Sun, 9 Sep 2012 21:46:26 +0000 (+0200) Subject: Clean up X-Git-Tag: 24jan2021_ls180~2575^2~156 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4a59b631514c3898132e01c29df175f592b9ef98;p=litex.git Clean up --- diff --git a/README b/README index 7c968f1d..8b93ce0b 100644 --- a/README +++ b/README @@ -7,5 +7,15 @@ or external signals. [> Status: Early development phase +Simulation: +-tb_spi2Csr : Test Spi <--> Csr Bridge : [Ok] +-tb_TriggerCsr : Test Trigger with Csr : [Ok] +-tb_RecorderCsr : Test Recorder with Csr : [Ok] +-tb_MigScope : Global Test with Csr : [Ok] + +Example Design: +-de0_nano : Generate Signals in FPGA and probe them with migScope : [Wip] + + [> Contact E-mail: florent@enjoy-digital.fr diff --git a/examples/de0_nano/top.py b/examples/de0_nano/top.py index e37422ba..5d5abf73 100644 --- a/examples/de0_nano/top.py +++ b/examples/de0_nano/top.py @@ -11,13 +11,13 @@ # ---------------------------------- ################################################################################ # -# In this example, signals are generated inside generated inside the FPGA. -# We will use migScope to record those signals it and visualize them. +# In this example signals are generated in the FPGA. +# We will use migScope to record those signals and visualize them. # # Example architecture: # ---------------------- -# migScope Config <-- Python Client (Host) --> Vcd Output -# | +# migScope Config --> Python Client (Host) --> Vcd Output +# & Trig | # Arduino (Uart<-->Spi Bridge) # | # De0 Nano diff --git a/migScope/recorder.py b/migScope/recorder.py index a3366f9b..edbe1c29 100644 --- a/migScope/recorder.py +++ b/migScope/recorder.py @@ -135,7 +135,7 @@ class Recorder: self._offset = RegisterField("offset", self.depth_width, reset=1) self._get = RegisterField("get", reset=0) - self._get_dat = RegisterField("get_dat", self.width, reset=1,access_bus=READ_ONLY, access_dev=WRITE_ONLY) + self._get_dat = RegisterField("get_dat", self.width, reset=1, access_bus=READ_ONLY, access_dev=WRITE_ONLY) regs = [self._rst, self._arm, self._done, self._size, self._offset, diff --git a/migScope/tools/conv.py b/migScope/tools/conv.py index df6394d9..66b88db8 100644 --- a/migScope/tools/conv.py +++ b/migScope/tools/conv.py @@ -1,4 +1,4 @@ -def dec2bin(d,nb=0): +def dec2bin(d, nb=0): if d=="x": return "x"*nb elif d==0: diff --git a/migScope/tools/truthtable.py b/migScope/tools/truthtable.py index 6f091080..ed53e2d3 100644 --- a/migScope/tools/truthtable.py +++ b/migScope/tools/truthtable.py @@ -3,7 +3,7 @@ import re import sys def get_operands(s): - return sorted(re.findall("[A-z0-9_]+",s)) + return sorted(re.findall("[A-z0-9_]+", s)) def gen_truth_table(s): operands = get_operands(s) diff --git a/migScope/tools/vcd.py b/migScope/tools/vcd.py index d7b1246f..3d89188a 100644 --- a/migScope/tools/vcd.py +++ b/migScope/tools/vcd.py @@ -24,7 +24,7 @@ class Var: try : if self.values[cnt+1] != self.val: r += "b" - r += dec2bin(self.values[cnt+1],self.width) + r += dec2bin(self.values[cnt+1], self.width) r += " " r += self.vcd_id r += "\n" @@ -158,12 +158,12 @@ class Vcd: def main(): myvcd = Vcd() - myvcd.add(Var("wire",1,"foo1",[0,1,0,1,0,1])) - myvcd.add(Var("wire",2,"foo2",[1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0])) - myvcd.add(Var("wire",3,"foo3")) - myvcd.add(Var("wire",4,"foo4")) + myvcd.add(Var("wire", 1, "foo1", [0,1,0,1,0,1])) + myvcd.add(Var("wire", 2, "foo2", [1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0])) + myvcd.add(Var("wire", 3, "foo3")) + myvcd.add(Var("wire", 4, "foo4")) ramp = [i%128 for i in range(1024)] - myvcd.add(Var("wire",16,"ramp",ramp)) + myvcd.add(Var("wire", 16, "ramp", ramp)) print(myvcd) if __name__ == '__main__': diff --git a/migScope/trigger.py b/migScope/trigger.py index 3acf3c0b..2e9d1da9 100644 --- a/migScope/trigger.py +++ b/migScope/trigger.py @@ -209,7 +209,7 @@ class Sum: sync += [self.o.eq(self._o)] else: comb += [self.o.eq(self._o)] - return Fragment(comb=comb,sync=sync,memories=memories) + return Fragment(comb=comb, sync=sync, memories=memories) def connect_to_reg(self, reg): comb = [] @@ -242,7 +242,7 @@ class Trigger: for port in self.ports: setattr(self,port.reg_name,RegisterField(port.reg_name, port.reg_size, reset=0, access_bus=WRITE_ONLY, access_dev=READ_ONLY)) - self.sum_reg = RegisterField(self.sum.reg_name, self.sum.reg_size, reset=0,access_bus=WRITE_ONLY, access_dev=READ_ONLY) + self.sum_reg = RegisterField(self.sum.reg_name, self.sum.reg_size, reset=0, access_bus=WRITE_ONLY, access_dev=READ_ONLY) regs = [] objects = self.__dict__ diff --git a/sim/tb_Migscope.py b/sim/tb_Migscope.py index 8cf51345..8f55bbad 100644 --- a/sim/tb_Migscope.py +++ b/sim/tb_Migscope.py @@ -41,10 +41,10 @@ def csr_transactions(trigger0, recorder0): # Term Prog term_trans = [] - term_trans += [term_prog(trigger0.ports[0].reg_base,0x00000000)] - term_trans += [term_prog(trigger0.ports[1].reg_base,0x00000004)] - term_trans += [term_prog(trigger0.ports[2].reg_base,0x00000008)] - term_trans += [term_prog(trigger0.ports[3].reg_base,0x0000000C)] + term_trans += [term_prog(trigger0.ports[0].reg_base, 0x00000000)] + term_trans += [term_prog(trigger0.ports[1].reg_base, 0x00000004)] + term_trans += [term_prog(trigger0.ports[2].reg_base, 0x00000008)] + term_trans += [term_prog(trigger0.ports[3].reg_base, 0x0000000C)] for t in term_trans: for r in t: yield r @@ -53,7 +53,7 @@ def csr_transactions(trigger0, recorder0): sum_tt = gen_truth_table("term0 | term1 | term2 | term3") sum_trans = [] for i in range(len(sum_tt)): - sum_trans.append(sum_prog(trigger0.sum.reg_base,i,sum_tt[i])) + sum_trans.append(sum_prog(trigger0.sum.reg_base, i, sum_tt[i])) for t in sum_trans: for r in t: yield r @@ -151,7 +151,7 @@ def main(): global dat_rdy if dat_rdy: print("%08X" %s.rd(recorder0._get_dat.field.w)) - global dat_vcd + global dat_vcd dat_vcd.append(s.rd(recorder0._get_dat.field.w)) @@ -159,8 +159,8 @@ def main(): def end_simulation(s): s.interrupt = csr_master0.done myvcd = Vcd() - myvcd.add(Var("wire",32,"trig_dat",dat_vcd)) - f = open("tb_Miscope_Out.vcd","w") + myvcd.add(Var("wire", 32, "trig_dat", dat_vcd)) + f = open("tb_Miscope_Out.vcd", "w") f.write(str(myvcd)) f.close() diff --git a/sim/tb_RecorderCsr.py b/sim/tb_RecorderCsr.py index 1fa6b8bf..e36d7844 100644 --- a/sim/tb_RecorderCsr.py +++ b/sim/tb_RecorderCsr.py @@ -45,7 +45,7 @@ def csr_transactions(): while not rec_done: yield None - global dat_rdy + global dat_rdy for t in range(32): yield TWrite(7, 1) dat_rdy = False @@ -66,10 +66,10 @@ def main(): csr_master0 = csr.Initiator(csr_transactions()) # Recorder - recorder0 = recorder.Recorder(0,32,1024) + recorder0 = recorder.Recorder(0, 32, 1024) # Csr Interconnect - csrcon0 = csr.Interconnect(csr_master0.bus, + csrcon0 = csr.Interconnect(csr_master0.bus, [ recorder0.bank.interface ]) @@ -78,7 +78,7 @@ def main(): def recorder_data(s): global arm_done if arm_done: - s.wr(recorder0.trig_hit,1) + s.wr(recorder0.trig_hit, 1) arm_done = False global trig_dat @@ -100,7 +100,7 @@ def main(): fragment = autofragment.from_local() fragment += Fragment(sim=[end_simulation]) fragment += Fragment(sim=[recorder_data]) - sim = Simulator(fragment, Runner(),TopLevel("tb_RecorderCsr.vcd")) + sim = Simulator(fragment, Runner(), TopLevel("tb_RecorderCsr.vcd")) sim.run(10000) main() diff --git a/sim/tb_TriggerCsr.py b/sim/tb_TriggerCsr.py index 3bf02785..eb2f8d1d 100644 --- a/sim/tb_TriggerCsr.py +++ b/sim/tb_TriggerCsr.py @@ -16,7 +16,6 @@ def term_prog(off, dat): for i in range(4): yield TWrite(off+3-i, (dat>>(8*i))&0xFF) - def sum_prog(off, addr, dat): we = 2 yield TWrite(off+3, addr%0xFF) @@ -39,18 +38,18 @@ def csr_transactions(): for t in term_trans: for r in t: yield r - + sum_trans = [] - sum_trans += [sum_prog(0x00,i,1) for i in range(8)] - sum_trans += [sum_prog(0x00,i,0) for i in range(8)] + sum_trans += [sum_prog(0x00, i, 1) for i in range(8)] + sum_trans += [sum_prog(0x00, i, 0) for i in range(8)] for t in sum_trans: for r in t: yield r - + sum_tt = gen_truth_table("i1 & i2 & i3 & i4") sum_trans = [] for i in range(len(sum_tt)): - sum_trans.append(sum_prog(0x00,i,sum_tt[i])) + sum_trans.append(sum_prog(0x00, i, sum_tt[i])) print(sum_tt) for t in sum_trans: for r in t: @@ -66,7 +65,7 @@ def csr_transactions(): def main(): # Csr Master csr_master0 = csr.Initiator(csr_transactions()) - + # Trigger term0 = trigger.Term(32) term1 = trigger.Term(32) @@ -79,24 +78,24 @@ def main(): [ trigger0.bank.interface ]) - + # Term Test def term_stimuli(s): if csr_done: - s.wr(term0.i,0xDEADBEEF) - s.wr(term1.i,0xCAFEFADE) - s.wr(term2.i,0xDEADBEEF) - s.wr(term3.i,0xCAFEFADE) - + s.wr(term0.i, 0xDEADBEEF) + s.wr(term1.i ,0xCAFEFADE) + s.wr(term2.i, 0xDEADBEEF) + s.wr(term3.i, 0xCAFEFADE) + # Simulation def end_simulation(s): s.interrupt = csr_master0.done - + fragment = autofragment.from_local() fragment += Fragment(sim=[end_simulation]) fragment += Fragment(sim=[term_stimuli]) - sim = Simulator(fragment, Runner(),TopLevel("tb_TriggerCsr.vcd")) + sim = Simulator(fragment, Runner(), TopLevel("tb_TriggerCsr.vcd")) sim.run(2000) main() diff --git a/sim/tb_spi2Csr.py b/sim/tb_spi2Csr.py index cee3925c..ef3b2d6b 100644 --- a/sim/tb_spi2Csr.py +++ b/sim/tb_spi2Csr.py @@ -22,15 +22,15 @@ def spi_transactions(): yield TWrite(0x0001, 0xA5) yield TWrite(0x0002, 0x5A) yield TWrite(0x0003, 0xA5) - + for i in range(10): yield None - + yield TRead(0x0000) yield TRead(0x0001) yield TRead(0x0002) yield TRead(0x0003) - + for i in range(100): yield None @@ -47,7 +47,7 @@ class SpiMaster(PureSimulable): def do_simulation(self, s): a_w = self.spi.a_width d_w = self.spi.d_width - + if not self.done: if self.transaction is None: try: @@ -66,7 +66,7 @@ class SpiMaster(PureSimulable): s.wr(self.spi.spi_clk, 1) else: s.wr(self.spi.spi_clk, 0) - + # Mosi Addr if self.transaction_cnt < a_w*self.clk_ratio: bit = a_w-1-int((self.transaction_cnt)/self.clk_ratio) @@ -82,7 +82,7 @@ class SpiMaster(PureSimulable): s.wr(self.spi.spi_mosi, data) else: s.wr(self.spi.spi_mosi, 0) - + # Cs_n if self.transaction_cnt < (a_w + d_w)*self.clk_ratio: s.wr(self.spi.spi_cs_n,0) @@ -91,10 +91,10 @@ class SpiMaster(PureSimulable): s.wr(self.spi.spi_clk, 0) s.wr(self.spi.spi_mosi, 0) self.transaction = None - + # Incr transaction_cnt self.transaction_cnt +=1 - + elif isinstance(self.transaction, TRead): # Clk @@ -102,7 +102,7 @@ class SpiMaster(PureSimulable): s.wr(self.spi.spi_clk, 1) else: s.wr(self.spi.spi_clk, 0) - + # Mosi Addr if self.transaction_cnt < a_w*self.clk_ratio: bit = a_w-1-int((self.transaction_cnt)/self.clk_ratio) @@ -119,7 +119,7 @@ class SpiMaster(PureSimulable): bit = d_w-1-int((self.transaction_cnt-a_w*self.clk_ratio)/self.clk_ratio) if s.rd(self.spi.spi_miso): self.r_dat = set_bit(self.r_dat, bit) - + # Cs_n if self.transaction_cnt < (a_w + d_w)*self.clk_ratio: s.wr(self.spi.spi_cs_n,0) @@ -129,12 +129,11 @@ class SpiMaster(PureSimulable): s.wr(self.spi.spi_mosi, 0) self.transaction = None print("%02X" %self.r_dat) - + # Incr transaction_cnt self.transaction_cnt +=1 - def main(): # Csr Slave scratch_reg0 = RegisterField("scratch_reg0", 32, reset=0, access_dev=READ_ONLY) @@ -143,11 +142,11 @@ def main(): scratch_reg3 = RegisterField("scratch_reg4", 32, reset=0, access_dev=READ_ONLY) regs = [scratch_reg0, scratch_reg1, scratch_reg2, scratch_reg3] bank0 = csrgen.Bank(regs,address=0x0000) - + # Spi2Csr spi2csr0 = spi2Csr.Spi2Csr(16,8) - - + + # Csr Interconnect csrcon0 = csr.Interconnect(spi2csr0.csr, [ @@ -156,12 +155,12 @@ def main(): # Spi Master spi_master0 = SpiMaster(spi2csr0, 8, spi_transactions()) - + # Simulation def end_simulation(s): s.interrupt = spi_master0.done - - + + fragment = autofragment.from_local() fragment += Fragment(sim=[end_simulation]) sim = Simulator(fragment, Runner(),TopLevel("tb_spi2Csr.vcd"))