From: lkcl Date: Sat, 30 Apr 2022 20:05:06 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~2529 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4a59de4ec422af8218a8fa9cded13123670d5e01;p=libreriscv.git --- diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index add177fc2..12deeaccf 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -987,7 +987,7 @@ overlap. It is extremely important for implementors to note that the only circumstance where upper portions of an underlying 64-bit register are zero'd out is when the destination is a scalar. The ideal register file has byte-level -write-enable lines, just like most SRAMs. +write-enable lines, just like most SRAMs, in order to avoid READ-MODIFY-WRITE. An example ADD operation with predication and element width overrides: @@ -1002,6 +1002,10 @@ An example ADD operation with predication and element width overrides: if (RA.isvec)  { irs1 += 1; } if (RB.isvec)  { irs2 += 1; } +Thus it can be clearly seen that elements are packed by their +element width, and the packing starts from the source (or destination) +specified by the instruction. + # Twin (implicit) result operations Some operations in the Power ISA already target two 64-bit scalar