From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 3 Nov 2013 08:00:51 +0000 (+0100)
Subject: Ignore explicit unconnected ports in intersynth backend
X-Git-Tag: yosys-0.2.0~419^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4a60e5842d6a39c5b1917b2a6b5f7433b08280a3;p=yosys.git

Ignore explicit unconnected ports in intersynth backend
---

diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index 83db8908c..a3f61eeb5 100644
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -174,9 +174,11 @@ struct IntersynthBackend : public Backend {
 				node_code = stringf("node %s %s", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
 				for (auto &port : cell->connections) {
 					RTLIL::SigSpec sig = sigmap(port.second);
-					conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.width, sig.width, sig.width));
-					celltype_code += stringf(" b%d %s%s", sig.width, ct.cell_output(cell->type, port.first) ? "*" : "", RTLIL::id2cstr(port.first));
-					node_code += stringf(" %s %s", RTLIL::id2cstr(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str());
+					if (sig.width != 0) {
+						conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.width, sig.width, sig.width));
+						celltype_code += stringf(" b%d %s%s", sig.width, ct.cell_output(cell->type, port.first) ? "*" : "", RTLIL::id2cstr(port.first));
+						node_code += stringf(" %s %s", RTLIL::id2cstr(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str());
+					}
 				}
 				for (auto &param : cell->parameters) {
 					celltype_code += stringf(" cfg:%d %s", int(param.second.bits.size()), RTLIL::id2cstr(param.first));